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KINETIS
KE1xF
fsl
fsl_ftfx_adapter.h
Go to the documentation of this file.
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/*
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* The Clear BSD License
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* Copyright 2017-2018 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted (subject to the limitations in the
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* disclaimer below) provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef _FSL_FTFX_ADAPTER_H_
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#define _FSL_FTFX_ADAPTER_H_
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define INVALID_REG_MASK (0)
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#define INVALID_REG_SHIFT (0)
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#define INVALID_REG_ADDRESS (0x00U)
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#define INVALID_REG_VALUE (0x00U)
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/* @brief Flash register access type defines */
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#define FTFx_REG8_ACCESS_TYPE volatile uint8_t *
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#define FTFx_REG32_ACCESS_TYPE volatile uint32_t *
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/*!
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* @name Common flash register info defines
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* @{
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*/
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#if defined(FTFA)
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#define FTFx FTFA
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#define FTFx_BASE FTFA_BASE
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#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK
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#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK
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#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK
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#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK
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#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK
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#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK
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#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK
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#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
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#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK
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#endif
/* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
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#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
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#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK
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#endif
/* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
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#elif defined(FTFE)
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#define FTFx FTFE
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#define FTFx_BASE FTFE_BASE
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#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK
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#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK
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#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK
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#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK
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#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK
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#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK
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#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK
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#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
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#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK
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#endif
/* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
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#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
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#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK
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#endif
/* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
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#elif defined(FTFL)
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#define FTFx FTFL
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#define FTFx_BASE FTFL_BASE
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#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK
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#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK
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#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK
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#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK
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#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK
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#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK
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#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK
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#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM
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#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK
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#endif
/* FSL_FEATURE_FLASH_HAS_FLEX_RAM */
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#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM
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#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK
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#endif
/* FSL_FEATURE_FLASH_HAS_FLEX_NVM */
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#else
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#error "Unknown flash controller"
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#endif
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/*@}*/
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/*!
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* @name Common flash register access info defines
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* @{
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*/
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#define FTFx_FCCOB3_REG (FTFx->FCCOB3)
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#define FTFx_FCCOB5_REG (FTFx->FCCOB5)
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#define FTFx_FCCOB6_REG (FTFx->FCCOB6)
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#define FTFx_FCCOB7_REG (FTFx->FCCOB7)
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#if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK)
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#define FTFx_FLASH1_HAS_INT_PROT_REG (1)
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#define FTFx_FPROTSH_REG (FTFx->FPROTSH)
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#define FTFx_FPROTSL_REG (FTFx->FPROTSL)
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#else
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#define FTFx_FLASH1_HAS_INT_PROT_REG (0)
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#define FTFx_FPROTSH_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTSL_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#endif
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#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK)
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#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3)
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#define FTFx_FPROTH3_REG (FTFx->FPROTH3)
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#define FTFx_FPROTH2_REG (FTFx->FPROTH2)
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#define FTFx_FPROTH1_REG (FTFx->FPROTH1)
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#define FTFx_FPROTH0_REG (FTFx->FPROTH0)
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#else
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#define FTFx_FPROT_HIGH_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTH3_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTH2_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTH1_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTH0_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#endif
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#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK)
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#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3)
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#define FTFx_FPROTL3_REG (FTFx->FPROTL3)
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#define FTFx_FPROTL2_REG (FTFx->FPROTL2)
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#define FTFx_FPROTL1_REG (FTFx->FPROTL1)
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#define FTFx_FPROTL0_REG (FTFx->FPROTL0)
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#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK)
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#define FTFx_FPROT_LOW_REG (FTFx->FPROT3)
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#define FTFx_FPROTL3_REG (FTFx->FPROT3)
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#define FTFx_FPROTL2_REG (FTFx->FPROT2)
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#define FTFx_FPROTL1_REG (FTFx->FPROT1)
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#define FTFx_FPROTL0_REG (FTFx->FPROT0)
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#else
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#define FTFx_FPROT_LOW_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTL3_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTL2_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTL1_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FPROTL0_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#endif
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#if defined(FTFA_FACSSS_SGSIZE_S_MASK) || defined(FTFE_FACSSS_SGSIZE_S_MASK) || defined(FTFL_FACSSS_SGSIZE_S_MASK)
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#define FTFx_FLASH1_HAS_INT_XACC_REG (1)
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#define FTFx_XACCSH_REG (FTFx->XACCSH)
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#define FTFx_XACCSL_REG (FTFx->XACCSL)
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#define FTFx_FACSSS_REG (FTFx->FACSSS)
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#define FTFx_FACSNS_REG (FTFx->FACSNS)
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#else
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#define FTFx_FLASH1_HAS_INT_XACC_REG (0)
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#define FTFx_XACCSH_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_XACCSL_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FACSSS_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FACSNS_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#endif
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#if (defined(FTFA_FACSS_SGSIZE_MASK) || defined(FTFE_FACSS_SGSIZE_MASK) || defined(FTFL_FACSS_SGSIZE_MASK) || \
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defined(FTFA_FACSS_SGSIZE_S_MASK) || defined(FTFE_FACSS_SGSIZE_S_MASK) || defined(FTFL_FACSS_SGSIZE_S_MASK))
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//#define FTFx_FLASH0_HAS_INT_XACC_REG (FTFx_FLASH1_HAS_INT_XACC_REG)
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#define FTFx_XACCH3_REG (FTFx->XACCH3)
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#define FTFx_XACCL3_REG (FTFx->XACCL3)
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#define FTFx_FACSS_REG (FTFx->FACSS)
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#define FTFx_FACSN_REG (FTFx->FACSN)
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#else
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#define FTFx_FLASH0_HAS_INT_XACC_REG (0)
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#define FTFx_XACCH3_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_XACCL3_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FACSS_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#define FTFx_FACSN_REG (*(uint8_t *)INVALID_REG_ADDRESS)
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#endif
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/*@}*/
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/*!
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* @brief MCM cache register access info defines.
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*/
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#if defined(MCM_PLACR_CFCC_MASK)
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#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK
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#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT
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#if defined(MCM0)
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#define MCM0_CACHE_REG MCM0->PLACR
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#elif defined(MCM) && (!defined(MCM1))
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#define MCM0_CACHE_REG MCM->PLACR
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#endif
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#if defined(MCM1)
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#define MCM1_CACHE_REG MCM1->PLACR
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#elif defined(MCM) && (!defined(MCM0))
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#define MCM1_CACHE_REG MCM->PLACR
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#endif
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#else
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#define MCM_CACHE_CLEAR_MASK INVALID_REG_MASK
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#define MCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT
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#define MCM0_CACHE_REG (*(uint32_t *)INVALID_REG_ADDRESS)
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#define MCM1_CACHE_REG (*(uint32_t *)INVALID_REG_ADDRESS)
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#endif
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/*!
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* @brief FMC cache register access info defines.
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*/
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#if defined(FMC_PFB01CR_S_INV_MASK)
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#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_INV_MASK
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#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_INV_SHIFT
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#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR
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#elif defined(FMC_PFB01CR_S_B_INV_MASK)
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#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_B_INV_MASK
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#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
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#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR
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#elif defined(FMC_PFB0CR_S_INV_MASK)
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#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_INV_MASK
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#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_INV_SHIFT
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#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR
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#elif defined(FMC_PFB0CR_S_B_INV_MASK)
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#define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_B_INV_MASK
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#define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_B_INV_SHIFT
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#define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR
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#else
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#define FMC_SPECULATION_INVALIDATE_MASK INVALID_REG_MASK
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#define FMC_SPECULATION_INVALIDATE_SHIFT INVALID_REG_SHIFT
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#define FMC_SPECULATION_INVALIDATE(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
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#define FMC_SPECULATION_INVALIDATE_REG (*(uint32_t *)INVALID_REG_ADDRESS)
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#endif
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#if defined(FMC_PFB01CR_CINV_WAY_MASK)
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#define FMC_CACHE_CLEAR_MASK FMC_PFB01CR_CINV_WAY_MASK
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#define FMC_CACHE_CLEAR_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
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#define FMC_CACHE_CLEAR(x) FMC_PFB01CR_CINV_WAY(x)
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#elif defined(FMC_PFB0CR_CINV_WAY_MASK)
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#define FMC_CACHE_CLEAR_MASK FMC_PFB0CR_CINV_WAY_MASK
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#define FMC_CACHE_CLEAR_SHIFT FMC_PFB0CR_CINV_WAY_SHIFT
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#define FMC_CACHE_CLEAR(x) FMC_PFB0CR_CINV_WAY(x)
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#else
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#define FMC_CACHE_CLEAR_MASK INVALID_REG_MASK
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#define FMC_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT
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#define FMC_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
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#endif
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#if defined(FMC_PFB01CR_B0DPE_MASK)
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#define FMC_CACHE_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
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#define FMC_CACHE_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
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#define FMC_CACHE_REG FMC->PFB01CR
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#elif defined(FMC_PFB0CR_B0DPE_MASK)
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#define FMC_CACHE_B0DPE_MASK FMC_PFB0CR_B0DPE_MASK
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#define FMC_CACHE_B0IPE_MASK FMC_PFB0CR_B0IPE_MASK
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#define FMC_CACHE_REG FMC->PFB0CR
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#else
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#define FMC_CACHE_B0DPE_MASK INVALID_REG_MASK
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#define FMC_CACHE_B0IPE_MASK INVALID_REG_MASK
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#define FMC_CACHE_REG (*(uint32_t *)INVALID_REG_ADDRESS)
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#endif
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/*!
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* @brief MSCM cache register access info defines.
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*/
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#if defined(MSCM_OCMDR_OCM1_MASK)
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#define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCM1_MASK
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#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCM1_SHIFT
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#define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCM1(x)
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#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK)
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#define MSCM_SPECULATION_SET_MASK MSCM_OCMDR0_OCM1_MASK
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#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR0_OCM1_SHIFT
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#define MSCM_SPECULATION_SET(x) MSCM_OCMDR0_OCM1(x)
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#elif defined(MSCM_OCMDR_OCMC1_MASK)
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#define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCMC1_MASK
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#define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCMC1_SHIFT
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#define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCMC1(x)
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#else
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#define MSCM_SPECULATION_SET_MASK INVALID_REG_MASK
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#define MSCM_SPECULATION_SET_SHIFT INVALID_REG_SHIFT
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#define MSCM_SPECULATION_SET(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
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#endif
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#if defined(MSCM_OCMDR_OCM2_MASK)
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#define MSCM_CACHE_CLEAR_MASK MSCM_OCMDR_OCM2_MASK
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#define MSCM_CACHE_CLEAR_SHIFT MSCM_OCMDR_OCM2_SHIFT
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#define MSCM_CACHE_CLEAR(x) MSCM_OCMDR_OCM2(x)
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#else
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#define MSCM_CACHE_CLEAR_MASK INVALID_REG_MASK
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#define MSCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT
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#define MSCM_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)
299
#endif
300
301
#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK)
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#define MSCM_OCMDR0_REG MSCM->OCMDR[0]
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#define MSCM_OCMDR1_REG MSCM->OCMDR[1]
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#elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK)
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#define MSCM_OCMDR0_REG MSCM->OCMDR0
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#define MSCM_OCMDR1_REG MSCM->OCMDR1
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#else
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#define MSCM_OCMDR0_REG (*(uint32_t *)INVALID_REG_ADDRESS)
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#define MSCM_OCMDR1_REG (*(uint32_t *)INVALID_REG_ADDRESS)
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#endif
311
312
/*!
313
* @brief MSCM prefetch speculation defines.
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*/
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#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U)
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#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U)
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#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U)
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#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U)
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320
/*!
321
* @brief SIM PFSIZE register access info defines.
322
*/
323
#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK)
324
#define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_CORE0_PFSIZE_MASK
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#define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_CORE0_PFSIZE_SHIFT
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#define SIM_FCFG1_REG SIM->FCFG1
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#elif defined(SIM_FCFG1_PFSIZE_MASK)
328
#define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_PFSIZE_MASK
329
#define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_PFSIZE_SHIFT
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#define SIM_FCFG1_REG SIM->FCFG1
331
#else
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#define SIM_FLASH0_PFSIZE_MASK INVALID_REG_MASK
333
#define SIM_FLASH0_PFSIZE_SHIFT INVALID_REG_SHIFT
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#define SIM_FCFG1_REG INVALID_REG_VALUE
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#endif
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337
#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK)
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#define SIM_FLASH1_PFSIZE_MASK SIM_FCFG1_CORE1_PFSIZE_MASK
339
#define SIM_FLASH1_PFSIZE_SHIFT SIM_FCFG1_CORE1_PFSIZE_SHIFT
340
#else
341
#define SIM_FLASH1_PFSIZE_MASK INVALID_REG_MASK
342
#define SIM_FLASH1_PFSIZE_SHIFT INVALID_REG_SHIFT
343
#endif
344
345
/*!
346
* @name Dual core/flash configuration
347
* @{
348
*/
349
/*! @brief Redefines some flash features. */
350
#if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID)
351
#if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u)
352
#define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
353
#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
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#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE
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#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
356
#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
357
#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
358
#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
359
#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
360
#define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS
361
#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT
362
#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE
363
#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE
364
#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE
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#if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT)
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#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT
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#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT
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#else
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#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
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#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
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#endif
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#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT
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#elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u)
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#define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS
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#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT
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#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE
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#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE
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#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE
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#if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT)
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#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT
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#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT
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#else
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#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
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#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
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#endif
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#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT
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#define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
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#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
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#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE
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#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
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#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
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#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
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#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
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#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
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#endif
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#else
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#define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
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#define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
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#define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE
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#define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
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#define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE
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#define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT
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#define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT
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#define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT
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#define FLASH1_FEATURE_PFLASH_START_ADDRESS 0
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#define FLASH1_FEATURE_PFLASH_BLOCK_COUNT 0
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#define FLASH1_FEATURE_PFLASH_BLOCK_SIZE 0
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#define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE 0
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#define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE 0
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#define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 0
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#define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 0
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#define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 0
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#endif
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#if FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT > FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT
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#define MAX_FLASH_PROT_REGION_COUNT FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT
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#else
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#define MAX_FLASH_PROT_REGION_COUNT FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT
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#endif
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/*@}*/
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#endif
/* _FSL_FTFX_ADAPTER_H_ */
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