rusEFI
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board.h
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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * This file has been automatically generated using ChibiStudio board
19 * generator plugin. Do not edit manually.
20 */
21
22#ifndef BOARD_H
23#define BOARD_H
24
25/*===========================================================================*/
26/* Driver constants. */
27/*===========================================================================*/
28
29/*
30 * Board identifier.
31 */
32#define BOARD_NAME "H7 rusEFI"
33
34#define EFI_USB_AF 10U
35#define EFI_USB_SERIAL_DM Gpio::A11
36#define EFI_USB_SERIAL_DP Gpio::A12
37
38/*
39 * input-floating is the default pin mode. input-output boards should provision appropriate pull-ups/pull-downs.
40 */
41#define EFI_PIN_MODE_DEFAULT PIN_MODE_INPUT
42#ifndef EFI_DR_DEFAULT
43#define EFI_DR_DEFAULT PIN_PUPDR_PULLDOWN
44#endif
45
46// See https://github.com/rusefi/rusefi/issues/397
47#define DEFAULT_GPIO_SPEED PIN_OSPEED_HIGH
48
49
50/*
51 * Ethernet PHY type.
52 */
53#define BOARD_PHY_ID MII_LAN8742A_ID
54#define BOARD_PHY_RMII
55
56/*
57 * Board oscillators-related settings.
58 */
59#if !defined(STM32_LSECLK)
60#define STM32_LSECLK 32768U
61#endif
62
63#define STM32_LSEDRV (3U << 3U)
64
65#if !defined(STM32_HSECLK)
66#define STM32_HSECLK 8000000U
67#endif
68
69/*
70 * Board voltages.
71 * Required for performance limits calculation.
72 */
73#define STM32_VDD 330U
74
75/*
76 * MCU type as defined in the ST header.
77 */
78#ifndef STM32H743xx
79#define STM32H743xx
80#endif
81
82/*
83 * IO pins assignments.
84 */
85#define GPIOA_SWDIO 13
86#define GPIOA_SWCLK 14
87
88#define GPIOB_SWO 3
89
90#define VAL_GPIO_MODER_ALL_DEFAULT (EFI_PIN_MODE_DEFAULT(0) | \
91 EFI_PIN_MODE_DEFAULT(1) | \
92 EFI_PIN_MODE_DEFAULT(2) | \
93 EFI_PIN_MODE_DEFAULT(3) | \
94 EFI_PIN_MODE_DEFAULT(4) | \
95 EFI_PIN_MODE_DEFAULT(5) | \
96 EFI_PIN_MODE_DEFAULT(6) | \
97 EFI_PIN_MODE_DEFAULT(7) | \
98 EFI_PIN_MODE_DEFAULT(8) | \
99 EFI_PIN_MODE_DEFAULT(9) | \
100 EFI_PIN_MODE_DEFAULT(10) | \
101 EFI_PIN_MODE_DEFAULT(11) | \
102 EFI_PIN_MODE_DEFAULT(12) | \
103 EFI_PIN_MODE_DEFAULT(13) | \
104 EFI_PIN_MODE_DEFAULT(14) | \
105 EFI_PIN_MODE_DEFAULT(15))
106
107#define VAL_GPIO_OTYPER_ALL_DEFAULT (PIN_OTYPE_PUSHPULL(0) | \
108 PIN_OTYPE_PUSHPULL(1) | \
109 PIN_OTYPE_PUSHPULL(2) | \
110 PIN_OTYPE_PUSHPULL(3) | \
111 PIN_OTYPE_PUSHPULL(4) | \
112 PIN_OTYPE_PUSHPULL(5) | \
113 PIN_OTYPE_PUSHPULL(6) | \
114 PIN_OTYPE_PUSHPULL(7) | \
115 PIN_OTYPE_PUSHPULL(8) | \
116 PIN_OTYPE_PUSHPULL(9) | \
117 PIN_OTYPE_PUSHPULL(10) | \
118 PIN_OTYPE_PUSHPULL(11) | \
119 PIN_OTYPE_PUSHPULL(12) | \
120 PIN_OTYPE_PUSHPULL(13) | \
121 PIN_OTYPE_PUSHPULL(14) | \
122 PIN_OTYPE_PUSHPULL(15))
123
124#define VAL_GPIO_OSPEEDR_ALL_DEFAULT (DEFAULT_GPIO_SPEED(0) | \
125 DEFAULT_GPIO_SPEED(1) | \
126 DEFAULT_GPIO_SPEED(2) | \
127 DEFAULT_GPIO_SPEED(3) | \
128 DEFAULT_GPIO_SPEED(4) | \
129 DEFAULT_GPIO_SPEED(5) | \
130 DEFAULT_GPIO_SPEED(6) | \
131 DEFAULT_GPIO_SPEED(7) | \
132 DEFAULT_GPIO_SPEED(8) | \
133 DEFAULT_GPIO_SPEED(9) | \
134 DEFAULT_GPIO_SPEED(10) | \
135 DEFAULT_GPIO_SPEED(11) | \
136 DEFAULT_GPIO_SPEED(12) | \
137 DEFAULT_GPIO_SPEED(13) | \
138 DEFAULT_GPIO_SPEED(14) | \
139 DEFAULT_GPIO_SPEED(15))
140
141#define VAL_GPIO_ODR_ALL_DEFAULT 0
142
143#define VAL_GPIO_PUPDR_ALL_DEFAULT (EFI_DR_DEFAULT(0) | \
144 EFI_DR_DEFAULT(1) | \
145 EFI_DR_DEFAULT(2) | \
146 EFI_DR_DEFAULT(3) | \
147 EFI_DR_DEFAULT(4) | \
148 EFI_DR_DEFAULT(5) | \
149 EFI_DR_DEFAULT(6) | \
150 EFI_DR_DEFAULT(7) | \
151 EFI_DR_DEFAULT(8) | \
152 EFI_DR_DEFAULT(9) | \
153 EFI_DR_DEFAULT(10) | \
154 EFI_DR_DEFAULT(11) | \
155 EFI_DR_DEFAULT(12) | \
156 EFI_DR_DEFAULT(13) | \
157 EFI_DR_DEFAULT(14) | \
158 EFI_DR_DEFAULT(15))
159
160#define VAL_GPIO_AF_ALL_DEFAULT (PIN_AFIO_AF(0, 0U) | \
161 PIN_AFIO_AF(1, 0U) | \
162 PIN_AFIO_AF(2, 0U) | \
163 PIN_AFIO_AF(3, 0U) | \
164 PIN_AFIO_AF(4, 0U) | \
165 PIN_AFIO_AF(5, 0U) | \
166 PIN_AFIO_AF(6, 0U) | \
167 PIN_AFIO_AF(7, 0U))
168
169/*
170 * I/O ports initial setup, this configuration is established soon after reset
171 * in the initialization code.
172 * Please refer to the STM32 Reference Manual for details.
173 */
174#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
175#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
176#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
177#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
178#define PIN_ODR_LOW(n) (0U << (n))
179#define PIN_ODR_HIGH(n) (1U << (n))
180#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
181#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
182#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
183#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
184#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
185#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
186#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
187#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
188#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
189#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
190
191/*
192 * GPIOA setup:
193 *
194 * PA11 - OTG_FS_DM (alternate 10).
195 * PA12 - OTG_FS_DP (alternate 10).
196 * PA13 - SWDIO (alternate 0).
197 * PA14 - SWCLK (alternate 0).
198 */
199#define VAL_GPIOA_MODER (EFI_PIN_MODE_DEFAULT(0) | \
200 EFI_PIN_MODE_DEFAULT(1) | \
201 EFI_PIN_MODE_DEFAULT(2) | \
202 EFI_PIN_MODE_DEFAULT(3) | \
203 EFI_PIN_MODE_DEFAULT(4) | \
204 EFI_PIN_MODE_DEFAULT(5) | \
205 EFI_PIN_MODE_DEFAULT(6) | \
206 EFI_PIN_MODE_DEFAULT(7) | \
207 EFI_PIN_MODE_DEFAULT(8) | \
208 EFI_PIN_MODE_DEFAULT(9) | \
209 EFI_PIN_MODE_DEFAULT(10) | \
210 PIN_MODE_ALTERNATE(11) | \
211 PIN_MODE_ALTERNATE(12) | \
212 PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
213 PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
214 EFI_PIN_MODE_DEFAULT(15))
215#define VAL_GPIOA_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
216#define VAL_GPIOA_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
217#define VAL_GPIOA_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
218#define VAL_GPIOA_ODR VAL_GPIO_ODR_ALL_DEFAULT
219#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0U) | \
220 PIN_AFIO_AF(1, 0U) | \
221 PIN_AFIO_AF(2, 0U) | \
222 PIN_AFIO_AF(3, 0U) | \
223 PIN_AFIO_AF(4, 6U) | \
224 PIN_AFIO_AF(5, 5U) | \
225 PIN_AFIO_AF(6, 5U) | \
226 PIN_AFIO_AF(7, 5U))
227#define VAL_GPIOA_AFRH VAL_GPIO_AF_ALL_DEFAULT
228
229/*
230 * GPIOB setup:
231 *
232 * Default except SWO configured on PB3
233 *
234 */
235#define VAL_GPIOB_MODER (EFI_PIN_MODE_DEFAULT(0) | \
236 EFI_PIN_MODE_DEFAULT(1) | \
237 EFI_PIN_MODE_DEFAULT(2) | \
238 PIN_MODE_ALTERNATE(GPIOB_SWO) | \
239 EFI_PIN_MODE_DEFAULT(4) | \
240 EFI_PIN_MODE_DEFAULT(5) | \
241 EFI_PIN_MODE_DEFAULT(6) | \
242 EFI_PIN_MODE_DEFAULT(7) | \
243 EFI_PIN_MODE_DEFAULT(8) | \
244 EFI_PIN_MODE_DEFAULT(9) | \
245 EFI_PIN_MODE_DEFAULT(10) | \
246 EFI_PIN_MODE_DEFAULT(11) | \
247 EFI_PIN_MODE_DEFAULT(12) | \
248 EFI_PIN_MODE_DEFAULT(13) | \
249 EFI_PIN_MODE_DEFAULT(14) | \
250 EFI_PIN_MODE_DEFAULT(15))
251#define VAL_GPIOB_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
252#define VAL_GPIOB_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
253#define VAL_GPIOB_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
254#define VAL_GPIOB_ODR VAL_GPIO_ODR_ALL_DEFAULT
255#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0U) | \
256 PIN_AFIO_AF(1, 0U) | \
257 PIN_AFIO_AF(2, 0U) | \
258 PIN_AFIO_AF(GPIOB_SWO, 0U) | \
259 PIN_AFIO_AF(4, 0U) | \
260 PIN_AFIO_AF(5, 0U) | \
261 PIN_AFIO_AF(6, 0U) | \
262 PIN_AFIO_AF(7, 0U))
263#define VAL_GPIOB_AFRH VAL_GPIO_AF_ALL_DEFAULT
264
265/*
266 * GPIOC setup:
267 */
268#define VAL_GPIOC_MODER VAL_GPIO_MODER_ALL_DEFAULT
269#define VAL_GPIOC_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
270#define VAL_GPIOC_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
271#define VAL_GPIOC_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
272#define VAL_GPIOC_ODR VAL_GPIO_ODR_ALL_DEFAULT
273#define VAL_GPIOC_AFRL VAL_GPIO_AF_ALL_DEFAULT
274#define VAL_GPIOC_AFRH VAL_GPIO_AF_ALL_DEFAULT
275
276/*
277 * GPIOD setup:
278 */
279#define VAL_GPIOD_MODER VAL_GPIO_MODER_ALL_DEFAULT
280#define VAL_GPIOD_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
281#define VAL_GPIOD_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
282#define VAL_GPIOD_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
283#define VAL_GPIOD_ODR VAL_GPIO_ODR_ALL_DEFAULT
284#define VAL_GPIOD_AFRL VAL_GPIO_AF_ALL_DEFAULT
285#define VAL_GPIOD_AFRH VAL_GPIO_AF_ALL_DEFAULT
286
287/*
288 * GPIOE setup:
289 */
290#define VAL_GPIOE_MODER VAL_GPIO_MODER_ALL_DEFAULT
291#define VAL_GPIOE_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
292#define VAL_GPIOE_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
293#define VAL_GPIOE_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
294#define VAL_GPIOE_ODR VAL_GPIO_ODR_ALL_DEFAULT
295#define VAL_GPIOE_AFRL VAL_GPIO_AF_ALL_DEFAULT
296#define VAL_GPIOE_AFRH VAL_GPIO_AF_ALL_DEFAULT
297
298/*
299 * GPIOF setup:
300 */
301#define VAL_GPIOF_MODER VAL_GPIO_MODER_ALL_DEFAULT
302#define VAL_GPIOF_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
303#define VAL_GPIOF_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
304#define VAL_GPIOF_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
305#define VAL_GPIOF_ODR VAL_GPIO_ODR_ALL_DEFAULT
306#define VAL_GPIOF_AFRL VAL_GPIO_AF_ALL_DEFAULT
307#define VAL_GPIOF_AFRH VAL_GPIO_AF_ALL_DEFAULT
308
309/*
310 * GPIOG setup:
311 */
312#define VAL_GPIOG_MODER VAL_GPIO_MODER_ALL_DEFAULT
313#define VAL_GPIOG_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
314#define VAL_GPIOG_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
315#define VAL_GPIOG_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
316#define VAL_GPIOG_ODR VAL_GPIO_ODR_ALL_DEFAULT
317#define VAL_GPIOG_AFRL VAL_GPIO_AF_ALL_DEFAULT
318#define VAL_GPIOG_AFRH VAL_GPIO_AF_ALL_DEFAULT
319
320/*
321 * GPIOH setup:
322 */
323#define VAL_GPIOH_MODER VAL_GPIO_MODER_ALL_DEFAULT
324#define VAL_GPIOH_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
325#define VAL_GPIOH_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
326#define VAL_GPIOH_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
327#define VAL_GPIOH_ODR VAL_GPIO_ODR_ALL_DEFAULT
328#define VAL_GPIOH_AFRL VAL_GPIO_AF_ALL_DEFAULT
329#define VAL_GPIOH_AFRH VAL_GPIO_AF_ALL_DEFAULT
330
331/*
332 * GPIOI setup:
333 */
334#define VAL_GPIOI_MODER VAL_GPIO_MODER_ALL_DEFAULT
335#define VAL_GPIOI_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
336#define VAL_GPIOI_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
337#define VAL_GPIOI_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
338#define VAL_GPIOI_ODR VAL_GPIO_ODR_ALL_DEFAULT
339#define VAL_GPIOI_AFRL VAL_GPIO_AF_ALL_DEFAULT
340#define VAL_GPIOI_AFRH VAL_GPIO_AF_ALL_DEFAULT
341
342/*
343 * GPIOJ setup:
344 */
345#define VAL_GPIOJ_MODER VAL_GPIO_MODER_ALL_DEFAULT
346#define VAL_GPIOJ_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
347#define VAL_GPIOJ_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
348#define VAL_GPIOJ_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
349#define VAL_GPIOJ_ODR VAL_GPIO_ODR_ALL_DEFAULT
350#define VAL_GPIOJ_AFRL VAL_GPIO_AF_ALL_DEFAULT
351#define VAL_GPIOJ_AFRH VAL_GPIO_AF_ALL_DEFAULT
352
353/*
354 * GPIOK setup:
355 */
356#define VAL_GPIOK_MODER VAL_GPIO_MODER_ALL_DEFAULT
357#define VAL_GPIOK_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
358#define VAL_GPIOK_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
359#define VAL_GPIOK_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
360#define VAL_GPIOK_ODR VAL_GPIO_ODR_ALL_DEFAULT
361#define VAL_GPIOK_AFRL VAL_GPIO_AF_ALL_DEFAULT
362#define VAL_GPIOK_AFRH VAL_GPIO_AF_ALL_DEFAULT
363
364/*===========================================================================*/
365/* External declarations. */
366/*===========================================================================*/
367
368#if !defined(_FROM_ASM_)
369#ifdef __cplusplus
370extern "C" {
371#endif
372 void boardInit(void);
373#ifdef __cplusplus
374}
375#endif
376#endif /* _FROM_ASM_ */
377
378#endif /* BOARD_H */
boardInit
void boardInit(void)
Board-specific initialization code.
Definition board.c:31
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