rusEFI
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board.h
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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/*
18 * This file has been automatically generated using ChibiStudio board
19 * generator plugin. Do not edit manually.
20 */
21
22#ifndef BOARD_H
23#define BOARD_H
24
25/*===========================================================================*/
26/* Driver constants. */
27/*===========================================================================*/
28
29/*
30 * Board identifier.
31 */
32#define BOARD_NAME "H7 rusEFI"
33
34#define EFI_USB_AF 10U
35#define EFI_USB_SERIAL_DM Gpio::A11
36#define EFI_USB_SERIAL_DP Gpio::A12
37
38/*
39 * input-floating is the default pin mode. input-output boards should provision appropriate pull-ups/pull-downs.
40 */
41#define EFI_PIN_MODE_DEFAULT PIN_MODE_INPUT
42#ifndef EFI_DR_DEFAULT
43#define EFI_DR_DEFAULT PIN_PUPDR_PULLDOWN
44#endif
45
46// See https://github.com/rusefi/rusefi/issues/397
47#define DEFAULT_GPIO_SPEED PIN_OSPEED_HIGH
48
49
50/*
51 * Ethernet PHY type.
52 */
53#define BOARD_PHY_ID MII_LAN8742A_ID
54#define BOARD_PHY_RMII
55
56/*
57 * Board oscillators-related settings.
58 */
59#if !defined(STM32_LSECLK)
60#define STM32_LSECLK 32768U
61#endif
62
63#define STM32_LSEDRV (3U << 3U)
64
65#if !defined(STM32_HSECLK)
66#define STM32_HSECLK 8000000U
67#endif
68
69/*
70 * Board voltages.
71 * Required for performance limits calculation.
72 */
73#define STM32_VDD 330U
74
75/*
76 * IO pins assignments.
77 */
78#define GPIOA_SWDIO 13
79#define GPIOA_SWCLK 14
80
81#define GPIOB_SWO 3
82
83#define VAL_GPIO_MODER_ALL_DEFAULT (EFI_PIN_MODE_DEFAULT(0) | \
84 EFI_PIN_MODE_DEFAULT(1) | \
85 EFI_PIN_MODE_DEFAULT(2) | \
86 EFI_PIN_MODE_DEFAULT(3) | \
87 EFI_PIN_MODE_DEFAULT(4) | \
88 EFI_PIN_MODE_DEFAULT(5) | \
89 EFI_PIN_MODE_DEFAULT(6) | \
90 EFI_PIN_MODE_DEFAULT(7) | \
91 EFI_PIN_MODE_DEFAULT(8) | \
92 EFI_PIN_MODE_DEFAULT(9) | \
93 EFI_PIN_MODE_DEFAULT(10) | \
94 EFI_PIN_MODE_DEFAULT(11) | \
95 EFI_PIN_MODE_DEFAULT(12) | \
96 EFI_PIN_MODE_DEFAULT(13) | \
97 EFI_PIN_MODE_DEFAULT(14) | \
98 EFI_PIN_MODE_DEFAULT(15))
99
100#define VAL_GPIO_OTYPER_ALL_DEFAULT (PIN_OTYPE_PUSHPULL(0) | \
101 PIN_OTYPE_PUSHPULL(1) | \
102 PIN_OTYPE_PUSHPULL(2) | \
103 PIN_OTYPE_PUSHPULL(3) | \
104 PIN_OTYPE_PUSHPULL(4) | \
105 PIN_OTYPE_PUSHPULL(5) | \
106 PIN_OTYPE_PUSHPULL(6) | \
107 PIN_OTYPE_PUSHPULL(7) | \
108 PIN_OTYPE_PUSHPULL(8) | \
109 PIN_OTYPE_PUSHPULL(9) | \
110 PIN_OTYPE_PUSHPULL(10) | \
111 PIN_OTYPE_PUSHPULL(11) | \
112 PIN_OTYPE_PUSHPULL(12) | \
113 PIN_OTYPE_PUSHPULL(13) | \
114 PIN_OTYPE_PUSHPULL(14) | \
115 PIN_OTYPE_PUSHPULL(15))
116
117#define VAL_GPIO_OSPEEDR_ALL_DEFAULT (DEFAULT_GPIO_SPEED(0) | \
118 DEFAULT_GPIO_SPEED(1) | \
119 DEFAULT_GPIO_SPEED(2) | \
120 DEFAULT_GPIO_SPEED(3) | \
121 DEFAULT_GPIO_SPEED(4) | \
122 DEFAULT_GPIO_SPEED(5) | \
123 DEFAULT_GPIO_SPEED(6) | \
124 DEFAULT_GPIO_SPEED(7) | \
125 DEFAULT_GPIO_SPEED(8) | \
126 DEFAULT_GPIO_SPEED(9) | \
127 DEFAULT_GPIO_SPEED(10) | \
128 DEFAULT_GPIO_SPEED(11) | \
129 DEFAULT_GPIO_SPEED(12) | \
130 DEFAULT_GPIO_SPEED(13) | \
131 DEFAULT_GPIO_SPEED(14) | \
132 DEFAULT_GPIO_SPEED(15))
133
134#define VAL_GPIO_ODR_ALL_DEFAULT 0
135
136#define VAL_GPIO_PUPDR_ALL_DEFAULT (EFI_DR_DEFAULT(0) | \
137 EFI_DR_DEFAULT(1) | \
138 EFI_DR_DEFAULT(2) | \
139 EFI_DR_DEFAULT(3) | \
140 EFI_DR_DEFAULT(4) | \
141 EFI_DR_DEFAULT(5) | \
142 EFI_DR_DEFAULT(6) | \
143 EFI_DR_DEFAULT(7) | \
144 EFI_DR_DEFAULT(8) | \
145 EFI_DR_DEFAULT(9) | \
146 EFI_DR_DEFAULT(10) | \
147 EFI_DR_DEFAULT(11) | \
148 EFI_DR_DEFAULT(12) | \
149 EFI_DR_DEFAULT(13) | \
150 EFI_DR_DEFAULT(14) | \
151 EFI_DR_DEFAULT(15))
152
153#define VAL_GPIO_AF_ALL_DEFAULT (PIN_AFIO_AF(0, 0U) | \
154 PIN_AFIO_AF(1, 0U) | \
155 PIN_AFIO_AF(2, 0U) | \
156 PIN_AFIO_AF(3, 0U) | \
157 PIN_AFIO_AF(4, 0U) | \
158 PIN_AFIO_AF(5, 0U) | \
159 PIN_AFIO_AF(6, 0U) | \
160 PIN_AFIO_AF(7, 0U))
161
162/*
163 * I/O ports initial setup, this configuration is established soon after reset
164 * in the initialization code.
165 * Please refer to the STM32 Reference Manual for details.
166 */
167#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
168#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
169#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
170#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
171#define PIN_ODR_LOW(n) (0U << (n))
172#define PIN_ODR_HIGH(n) (1U << (n))
173#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
174#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
175#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
176#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
177#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
178#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
179#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
180#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
181#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
182#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
183
184/*
185 * GPIOA setup:
186 *
187 * PA11 - OTG_FS_DM (alternate 10).
188 * PA12 - OTG_FS_DP (alternate 10).
189 * PA13 - SWDIO (alternate 0).
190 * PA14 - SWCLK (alternate 0).
191 */
192#define VAL_GPIOA_MODER (EFI_PIN_MODE_DEFAULT(0) | \
193 EFI_PIN_MODE_DEFAULT(1) | \
194 EFI_PIN_MODE_DEFAULT(2) | \
195 EFI_PIN_MODE_DEFAULT(3) | \
196 EFI_PIN_MODE_DEFAULT(4) | \
197 EFI_PIN_MODE_DEFAULT(5) | \
198 EFI_PIN_MODE_DEFAULT(6) | \
199 EFI_PIN_MODE_DEFAULT(7) | \
200 EFI_PIN_MODE_DEFAULT(8) | \
201 EFI_PIN_MODE_DEFAULT(9) | \
202 EFI_PIN_MODE_DEFAULT(10) | \
203 PIN_MODE_ALTERNATE(11) | \
204 PIN_MODE_ALTERNATE(12) | \
205 PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
206 PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
207 EFI_PIN_MODE_DEFAULT(15))
208#define VAL_GPIOA_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
209#define VAL_GPIOA_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
210#define VAL_GPIOA_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
211#define VAL_GPIOA_ODR VAL_GPIO_ODR_ALL_DEFAULT
212#define VAL_GPIOA_AFRL VAL_GPIO_AF_ALL_DEFAULT
213#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8, 0U) | \
214 PIN_AFIO_AF(9, 0U) | \
215 PIN_AFIO_AF(10, 0U) | \
216 PIN_AFIO_AF(11, 10U) | \
217 PIN_AFIO_AF(12, 10U) | \
218 PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
219 PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
220 PIN_AFIO_AF(15, 0U))
221
222/*
223 * GPIOB setup:
224 *
225 * Default except SWO configured on PB3
226 *
227 */
228#define VAL_GPIOB_MODER (EFI_PIN_MODE_DEFAULT(0) | \
229 EFI_PIN_MODE_DEFAULT(1) | \
230 EFI_PIN_MODE_DEFAULT(2) | \
231 PIN_MODE_ALTERNATE(GPIOB_SWO) | \
232 EFI_PIN_MODE_DEFAULT(4) | \
233 EFI_PIN_MODE_DEFAULT(5) | \
234 EFI_PIN_MODE_DEFAULT(6) | \
235 EFI_PIN_MODE_DEFAULT(7) | \
236 EFI_PIN_MODE_DEFAULT(8) | \
237 EFI_PIN_MODE_DEFAULT(9) | \
238 EFI_PIN_MODE_DEFAULT(10) | \
239 EFI_PIN_MODE_DEFAULT(11) | \
240 EFI_PIN_MODE_DEFAULT(12) | \
241 EFI_PIN_MODE_DEFAULT(13) | \
242 EFI_PIN_MODE_DEFAULT(14) | \
243 EFI_PIN_MODE_DEFAULT(15))
244#define VAL_GPIOB_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
245#define VAL_GPIOB_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
246#define VAL_GPIOB_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
247#define VAL_GPIOB_ODR VAL_GPIO_ODR_ALL_DEFAULT
248#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0U) | \
249 PIN_AFIO_AF(1, 0U) | \
250 PIN_AFIO_AF(2, 0U) | \
251 PIN_AFIO_AF(GPIOB_SWO, 0U) | \
252 PIN_AFIO_AF(4, 0U) | \
253 PIN_AFIO_AF(5, 0U) | \
254 PIN_AFIO_AF(6, 0U) | \
255 PIN_AFIO_AF(7, 0U))
256#define VAL_GPIOB_AFRH VAL_GPIO_AF_ALL_DEFAULT
257
258/*
259 * GPIOC setup:
260 */
261#define VAL_GPIOC_MODER VAL_GPIO_MODER_ALL_DEFAULT
262#define VAL_GPIOC_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
263#define VAL_GPIOC_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
264#define VAL_GPIOC_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
265#define VAL_GPIOC_ODR VAL_GPIO_ODR_ALL_DEFAULT
266#define VAL_GPIOC_AFRL VAL_GPIO_AF_ALL_DEFAULT
267#define VAL_GPIOC_AFRH VAL_GPIO_AF_ALL_DEFAULT
268
269/*
270 * GPIOD setup:
271 */
272#define VAL_GPIOD_MODER VAL_GPIO_MODER_ALL_DEFAULT
273#define VAL_GPIOD_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
274#define VAL_GPIOD_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
275#define VAL_GPIOD_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
276#define VAL_GPIOD_ODR VAL_GPIO_ODR_ALL_DEFAULT
277#define VAL_GPIOD_AFRL VAL_GPIO_AF_ALL_DEFAULT
278#define VAL_GPIOD_AFRH VAL_GPIO_AF_ALL_DEFAULT
279
280/*
281 * GPIOE setup:
282 */
283#define VAL_GPIOE_MODER VAL_GPIO_MODER_ALL_DEFAULT
284#define VAL_GPIOE_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
285#define VAL_GPIOE_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
286#define VAL_GPIOE_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
287#define VAL_GPIOE_ODR VAL_GPIO_ODR_ALL_DEFAULT
288#define VAL_GPIOE_AFRL VAL_GPIO_AF_ALL_DEFAULT
289#define VAL_GPIOE_AFRH VAL_GPIO_AF_ALL_DEFAULT
290
291/*
292 * GPIOF setup:
293 */
294#define VAL_GPIOF_MODER VAL_GPIO_MODER_ALL_DEFAULT
295#define VAL_GPIOF_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
296#define VAL_GPIOF_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
297#define VAL_GPIOF_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
298#define VAL_GPIOF_ODR VAL_GPIO_ODR_ALL_DEFAULT
299#define VAL_GPIOF_AFRL VAL_GPIO_AF_ALL_DEFAULT
300#define VAL_GPIOF_AFRH VAL_GPIO_AF_ALL_DEFAULT
301
302/*
303 * GPIOG setup:
304 */
305#define VAL_GPIOG_MODER VAL_GPIO_MODER_ALL_DEFAULT
306#define VAL_GPIOG_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
307#define VAL_GPIOG_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
308#define VAL_GPIOG_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
309#define VAL_GPIOG_ODR VAL_GPIO_ODR_ALL_DEFAULT
310#define VAL_GPIOG_AFRL VAL_GPIO_AF_ALL_DEFAULT
311#define VAL_GPIOG_AFRH VAL_GPIO_AF_ALL_DEFAULT
312
313/*
314 * GPIOH setup:
315 */
316#define VAL_GPIOH_MODER VAL_GPIO_MODER_ALL_DEFAULT
317#define VAL_GPIOH_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
318#define VAL_GPIOH_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
319#define VAL_GPIOH_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
320#define VAL_GPIOH_ODR VAL_GPIO_ODR_ALL_DEFAULT
321#define VAL_GPIOH_AFRL VAL_GPIO_AF_ALL_DEFAULT
322#define VAL_GPIOH_AFRH VAL_GPIO_AF_ALL_DEFAULT
323
324/*
325 * GPIOI setup:
326 */
327#define VAL_GPIOI_MODER VAL_GPIO_MODER_ALL_DEFAULT
328#define VAL_GPIOI_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
329#define VAL_GPIOI_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
330#define VAL_GPIOI_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
331#define VAL_GPIOI_ODR VAL_GPIO_ODR_ALL_DEFAULT
332#define VAL_GPIOI_AFRL VAL_GPIO_AF_ALL_DEFAULT
333#define VAL_GPIOI_AFRH VAL_GPIO_AF_ALL_DEFAULT
334
335/*
336 * GPIOJ setup:
337 */
338#define VAL_GPIOJ_MODER VAL_GPIO_MODER_ALL_DEFAULT
339#define VAL_GPIOJ_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
340#define VAL_GPIOJ_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
341#define VAL_GPIOJ_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
342#define VAL_GPIOJ_ODR VAL_GPIO_ODR_ALL_DEFAULT
343#define VAL_GPIOJ_AFRL VAL_GPIO_AF_ALL_DEFAULT
344#define VAL_GPIOJ_AFRH VAL_GPIO_AF_ALL_DEFAULT
345
346/*
347 * GPIOK setup:
348 */
349#define VAL_GPIOK_MODER VAL_GPIO_MODER_ALL_DEFAULT
350#define VAL_GPIOK_OTYPER VAL_GPIO_OTYPER_ALL_DEFAULT
351#define VAL_GPIOK_OSPEEDR VAL_GPIO_OSPEEDR_ALL_DEFAULT
352#define VAL_GPIOK_PUPDR VAL_GPIO_PUPDR_ALL_DEFAULT
353#define VAL_GPIOK_ODR VAL_GPIO_ODR_ALL_DEFAULT
354#define VAL_GPIOK_AFRL VAL_GPIO_AF_ALL_DEFAULT
355#define VAL_GPIOK_AFRH VAL_GPIO_AF_ALL_DEFAULT
356
357/*===========================================================================*/
358/* External declarations. */
359/*===========================================================================*/
360
361#if !defined(_FROM_ASM_)
362#ifdef __cplusplus
363extern "C" {
364#endif
365 void boardInit(void);
366#ifdef __cplusplus
367}
368#endif
369#endif /* _FROM_ASM_ */
370
371#endif /* BOARD_H */
boardInit
void boardInit(void)
Board-specific initialization code.
Definition board.c:31
Generated on Sun Oct 19 2025 00:11:06 for rusEFI by doxygen 1.9.8