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mcuconf_stm32h723.h
Go to the documentation of this file.
1/*
2 * Memory attributes settings.
3 */
4#define STM32_NOCACHE_ENABLE FALSE
5#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
6#define STM32_NOCACHE_RBAR 0x24000000U
7#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
8
9/*
10 * PWR system settings.
11 * Reading STM32 Reference Manual is required, settings in PWR_CR3 are
12 * very critical.
13 * Register constants are taken from the ST header.
14 */
15#define STM32_VOS STM32_VOS_SCALE0
16#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
17#define STM32_PWR_CR2 (PWR_CR2_BREN)
18#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
19#define STM32_PWR_CPUCR 0
20
21/*
22 * Clock tree static settings.
23 * Reading STM32 Reference Manual is required.
24 */
25#define STM32_HSI_ENABLED TRUE
26#define STM32_LSI_ENABLED TRUE
27#define STM32_CSI_ENABLED TRUE
28#define STM32_HSI48_ENABLED TRUE
29#define STM32_HSE_ENABLED TRUE
30#define STM32_LSE_ENABLED TRUE
31#define STM32_HSIDIV STM32_HSIDIV_DIV1
32
33/*
34 * PLLs static settings.
35 * Reading STM32 Reference Manual is required.
36 */
37#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
38#define STM32_PLLCFGR_MASK ~0
39#define STM32_PLL1_ENABLED TRUE
40#define STM32_PLL1_P_ENABLED TRUE
41#define STM32_PLL1_Q_ENABLED TRUE
42#define STM32_PLL1_R_ENABLED TRUE
43#define STM32_PLL1_DIVM_VALUE 5
44#define STM32_PLL1_DIVN_VALUE 104
45#define STM32_PLL1_FRACN_VALUE 0
46#define STM32_PLL1_DIVP_VALUE 1
47#define STM32_PLL1_DIVQ_VALUE 10
48#define STM32_PLL1_DIVR_VALUE 4
49#define STM32_PLL2_ENABLED TRUE
50#define STM32_PLL2_P_ENABLED TRUE
51#define STM32_PLL2_Q_ENABLED TRUE
52#define STM32_PLL2_R_ENABLED TRUE
53#define STM32_PLL2_DIVM_VALUE 5
54#define STM32_PLL2_DIVN_VALUE 160
55#define STM32_PLL2_FRACN_VALUE 0
56#define STM32_PLL2_DIVP_VALUE 40
57#define STM32_PLL2_DIVQ_VALUE 8
58#define STM32_PLL2_DIVR_VALUE 8
59#define STM32_PLL3_ENABLED TRUE
60#define STM32_PLL3_P_ENABLED TRUE
61#define STM32_PLL3_Q_ENABLED TRUE
62#define STM32_PLL3_R_ENABLED TRUE
63#define STM32_PLL3_DIVM_VALUE 5
64#define STM32_PLL3_DIVN_VALUE 96
65#define STM32_PLL3_FRACN_VALUE 0
66#define STM32_PLL3_DIVP_VALUE 10
67#define STM32_PLL3_DIVQ_VALUE 10
68#define STM32_PLL3_DIVR_VALUE 10
69
70/*
71 * Core clocks dynamic settings (can be changed at runtime).
72 * Reading STM32 Reference Manual is required.
73 */
74#define STM32_SW STM32_SW_PLL1_P_CK
75#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
76#define STM32_D1CPRE STM32_D1CPRE_DIV1
77#define STM32_D1HPRE STM32_D1HPRE_DIV2
78#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
79#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
80#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
81#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
82
83/*
84 * Peripherals clocks static settings.
85 * Reading STM32 Reference Manual is required.
86 */
87#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
88#define STM32_MCO1PRE_VALUE 4
89#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
90#define STM32_MCO2PRE_VALUE 4
91#define STM32_TIMPRE_ENABLE TRUE
92#define STM32_HRTIMSEL 0
93#define STM32_STOPKERWUCK 0
94#define STM32_STOPWUCK 0
95#define STM32_RTCPRE_VALUE 8
96#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
97#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
98#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK
99#define STM32_FMCSEL STM32_FMCSEL_HCLK
100#define STM32_SWPSEL STM32_SWPSEL_PCLK1
101#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
102#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
103#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
104#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
105#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
106#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
107#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
108#define STM32_CECSEL STM32_CECSEL_LSE_CK
109#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
110#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1
111#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
112#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2
113#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
114#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
115#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
116#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
117#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
118#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
119#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
120#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
121#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
122
123/*
124 * USB driver system settings.
125 */
126#define STM32_USB_USE_OTG2 TRUE
127#define STM32_USB_OTG2_IRQ_PRIORITY 14
128#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
129#define STM32_USB_HOST_WAKEUP_DURATION 2
130
131/*
132 * WSPI driver system settings.
133 */
134#define STM32_WSPI_USE_OCTOSPI1 FALSE
135#define STM32_WSPI_USE_OCTOSPI2 FALSE
136#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
137#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
138#define STM32_WSPI_OCTOSPI1_SSHIFT FALSE
139#define STM32_WSPI_OCTOSPI2_SSHIFT FALSE
140#define STM32_WSPI_OCTOSPI1_DHQC FALSE
141#define STM32_WSPI_OCTOSPI2_DHQC FALSE
142#define STM32_WSPI_OCTOSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
143#define STM32_WSPI_OCTOSPI2_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
144#define STM32_WSPI_OCTOSPI1_MDMA_PRIORITY 1
145#define STM32_WSPI_OCTOSPI2_MDMA_PRIORITY 1
146#define STM32_WSPI_OCTOSPI1_MDMA_IRQ_PRIORITY 10
147#define STM32_WSPI_OCTOSPI2_MDMA_IRQ_PRIORITY 10
148#define STM32_WSPI_DMA_ERROR_HOOK(wspip) osalSysHalt("MDMA failure")