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mcuconf_stm32h743.h
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1/*
2 * Memory attributes settings.
3 */
4#ifndef STM32_NOCACHE_ENABLE
5#define STM32_NOCACHE_ENABLE TRUE
6#endif
7#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
8#define STM32_NOCACHE_RBAR 0x30040000U
9#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
10
11/*
12 * PWR system settings.
13 * Reading STM32 Reference Manual is required, settings in PWR_CR3 are
14 * very critical.
15 * Register constants are taken from the ST header.
16 */
17#define STM32_VOS STM32_VOS_SCALE1
18#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
19#define STM32_PWR_CR2 (PWR_CR2_BREN)
20#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
21#define STM32_PWR_CPUCR 0
22
23/*
24 * Clock tree static settings.
25 * Reading STM32 Reference Manual is required.
26 */
27#define STM32_HSI_ENABLED TRUE
28#define STM32_LSI_ENABLED TRUE
29#define STM32_CSI_ENABLED TRUE
30#define STM32_HSI48_ENABLED TRUE
31#define STM32_HSE_ENABLED TRUE
32// see RUSEFI_STM32_LSE_WAIT_MAX
33#define STM32_LSE_ENABLED TRUE
34#define STM32_HSIDIV STM32_HSIDIV_DIV1
35
36/*
37 * PLLs static settings.
38 * Reading STM32 Reference Manual is required.
39 *
40 * Configured to use HSI to generate 400mhz, but we will reconfigure to use HSE
41 * with appropriate PLLx_DIVM values for the detected external frequency.
42 * See osc_detector.cpp
43 */
44#define STM32_PLLSRC STM32_PLLSRC_HSI_CK
45#define STM32_PLLCFGR_MASK ~0
46
47/* PLL1 output clock is 800 MHz */
48#define STM32_PLL1_ENABLED TRUE
49#define STM32_PLL1_P_ENABLED TRUE
50#define STM32_PLL1_Q_ENABLED TRUE
51#define STM32_PLL1_R_ENABLED TRUE
52#define STM32_PLL1_DIVM_VALUE 32
53#define STM32_PLL1_DIVN_VALUE 400
54#define STM32_PLL1_FRACN_VALUE 0
55#define STM32_PLL1_DIVP_VALUE 2
56#define STM32_PLL1_DIVQ_VALUE 4
57#define STM32_PLL1_DIVR_VALUE 2
58
59/* PLL2 output clock is 960 MHz */
60#define STM32_PLL2_ENABLED TRUE
61#define STM32_PLL2_P_ENABLED TRUE
62#define STM32_PLL2_Q_ENABLED TRUE
63#define STM32_PLL2_R_ENABLED TRUE
64#define STM32_PLL2_DIVM_VALUE 32
65#define STM32_PLL2_DIVN_VALUE 480
66#define STM32_PLL2_FRACN_VALUE 0
67#define STM32_PLL2_DIVP_VALUE 10
68#define STM32_PLL2_DIVQ_VALUE 12
69#define STM32_PLL2_DIVR_VALUE 20
70
71/* PLL3 output clock is 960 MHz */
72#define STM32_PLL3_ENABLED TRUE
73#define STM32_PLL3_P_ENABLED TRUE
74#define STM32_PLL3_Q_ENABLED TRUE
75#define STM32_PLL3_R_ENABLED TRUE
76#define STM32_PLL3_DIVM_VALUE 32
77#define STM32_PLL3_DIVN_VALUE 480
78#define STM32_PLL3_FRACN_VALUE 0
79#define STM32_PLL3_DIVP_VALUE 2
80#define STM32_PLL3_DIVQ_VALUE 20
81#define STM32_PLL3_DIVR_VALUE 12
82
83/*
84 * Core clocks dynamic settings (can be changed at runtime).
85 * Reading STM32 Reference Manual is required.
86 */
87#define STM32_SW STM32_SW_PLL1_P_CK
88// see RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL
89#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
90#define STM32_D1CPRE STM32_D1CPRE_DIV1
91#define STM32_D1HPRE STM32_D1HPRE_DIV2
92#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
93#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
94#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
95#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
96
97/*
98 * Peripherals clocks static settings.
99 * Reading STM32 Reference Manual is required.
100 */
101#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
102#define STM32_MCO1PRE_VALUE 4
103#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
104#define STM32_MCO2PRE_VALUE 4
105#define STM32_TIMPRE_ENABLE TRUE
106#define STM32_HRTIMSEL 0
107#define STM32_STOPKERWUCK 0
108#define STM32_STOPWUCK 0
109#define STM32_RTCPRE_VALUE 8
110#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
111#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL2_R_CK
112#define STM32_QSPISEL STM32_QSPISEL_HCLK
113#define STM32_FMCSEL STM32_QSPISEL_HCLK
114#define STM32_SWPSEL STM32_SWPSEL_PCLK1
115#define STM32_FDCANSEL STM32_FDCANSEL_PLL2_Q_CK
116#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
117#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
118#define STM32_SPI45SEL STM32_SPI45SEL_PLL2_Q_CK
119#define STM32_SPI123SEL STM32_SPI123SEL_PLL2_P_CK
120#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
121#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
122#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
123#define STM32_CECSEL STM32_CECSEL_LSE_CK
124#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
125#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1
126#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
127#define STM32_USART16SEL STM32_USART16SEL_PLL2_Q_CK
128#define STM32_USART234578SEL STM32_USART234578SEL_PLL2_Q_CK
129#define STM32_SPI6SEL STM32_SPI6SEL_PLL2_Q_CK
130#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
131#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
132#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK
133#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
134#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
135#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
136#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
137
138/*
139 * USB driver system settings.
140 */
141#define STM32_USB_USE_OTG1 TRUE
142#define STM32_USB_USE_OTG2 FALSE
143#define STM32_USB_OTG1_IRQ_PRIORITY 14
144#define STM32_USB_OTG2_IRQ_PRIORITY 14
145#define STM32_USB_OTG1_RX_FIFO_SIZE 512
146#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
147#define STM32_USB_HOST_WAKEUP_DURATION 2