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hw_layer
ports
stm32
stm32h7
cfg
mcuconf_stm32h743.h
Go to the documentation of this file.
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/*
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* Memory attributes settings.
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*/
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#ifndef STM32_NOCACHE_ENABLE
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#define STM32_NOCACHE_ENABLE TRUE
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#endif
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#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
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#define STM32_NOCACHE_RBAR 0x30040000U
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#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
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/*
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* PWR system settings.
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* Reading STM32 Reference Manual is required, settings in PWR_CR3 are
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* very critical.
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* Register constants are taken from the ST header.
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*/
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#define STM32_VOS STM32_VOS_SCALE1
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#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
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#define STM32_PWR_CR2 (PWR_CR2_BREN)
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#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
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#define STM32_PWR_CPUCR 0
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/*
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* Clock tree static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_CSI_ENABLED TRUE
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#define STM32_HSI48_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#ifndef STM32_LSE_ENABLED
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// see RUSEFI_STM32_LSE_WAIT_MAX
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#define STM32_LSE_ENABLED TRUE
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#endif
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#define STM32_HSIDIV STM32_HSIDIV_DIV1
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/*
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* PLLs static settings.
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* Reading STM32 Reference Manual is required.
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*
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* Configured to use HSI to generate 400mhz, but we will reconfigure to use HSE
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* with appropriate PLLx_DIVM values for the detected external frequency.
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* See osc_detector.cpp
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*/
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#define STM32_PLLSRC STM32_PLLSRC_HSI_CK
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#define STM32_PLLCFGR_MASK ~0
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/* PLL1 output clock is 800 MHz */
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#define STM32_PLL1_ENABLED TRUE
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#define STM32_PLL1_P_ENABLED TRUE
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#define STM32_PLL1_Q_ENABLED TRUE
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#define STM32_PLL1_R_ENABLED TRUE
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#define STM32_PLL1_DIVM_VALUE 32
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#define STM32_PLL1_DIVN_VALUE 400
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#define STM32_PLL1_FRACN_VALUE 0
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#define STM32_PLL1_DIVP_VALUE 2
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#define STM32_PLL1_DIVQ_VALUE 4
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#define STM32_PLL1_DIVR_VALUE 2
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/* PLL2 output clock is 960 MHz */
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#define STM32_PLL2_ENABLED TRUE
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#define STM32_PLL2_P_ENABLED TRUE
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#define STM32_PLL2_Q_ENABLED TRUE
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#define STM32_PLL2_R_ENABLED TRUE
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#define STM32_PLL2_DIVM_VALUE 32
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#define STM32_PLL2_DIVN_VALUE 480
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#define STM32_PLL2_FRACN_VALUE 0
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#define STM32_PLL2_DIVP_VALUE 10
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#define STM32_PLL2_DIVQ_VALUE 12
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#define STM32_PLL2_DIVR_VALUE 20
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/* PLL3 output clock is 960 MHz */
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#define STM32_PLL3_ENABLED TRUE
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#define STM32_PLL3_P_ENABLED TRUE
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#define STM32_PLL3_Q_ENABLED TRUE
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#define STM32_PLL3_R_ENABLED TRUE
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#define STM32_PLL3_DIVM_VALUE 32
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#define STM32_PLL3_DIVN_VALUE 480
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#define STM32_PLL3_FRACN_VALUE 0
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#define STM32_PLL3_DIVP_VALUE 2
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#define STM32_PLL3_DIVQ_VALUE 20
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#define STM32_PLL3_DIVR_VALUE 12
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/*
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* Core clocks dynamic settings (can be changed at runtime).
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_SW STM32_SW_PLL1_P_CK
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// see RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL
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#if (STM32_LSE_ENABLED == TRUE)
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#define STM32_RTCSEL STM32_RTCSEL_LSE_CK
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#else
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#define STM32_RTCSEL STM32_RTCSEL_LSI_CK
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#endif
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#define STM32_D1CPRE STM32_D1CPRE_DIV1
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#define STM32_D1HPRE STM32_D1HPRE_DIV2
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#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
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#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
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#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
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#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
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/*
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* Peripherals clocks static settings.
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* Reading STM32 Reference Manual is required.
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*/
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
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#define STM32_MCO1PRE_VALUE 4
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#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
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#define STM32_MCO2PRE_VALUE 4
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#define STM32_TIMPRE_ENABLE TRUE
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#define STM32_HRTIMSEL 0
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#define STM32_STOPKERWUCK 0
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#define STM32_STOPWUCK 0
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#define STM32_RTCPRE_VALUE 8
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#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
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#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL2_R_CK
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#define STM32_QSPISEL STM32_QSPISEL_HCLK
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#define STM32_FMCSEL STM32_QSPISEL_HCLK
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#define STM32_SWPSEL STM32_SWPSEL_PCLK1
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#define STM32_FDCANSEL STM32_FDCANSEL_PLL2_Q_CK
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#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
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#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
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#define STM32_SPI45SEL STM32_SPI45SEL_PLL2_Q_CK
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#define STM32_SPI123SEL STM32_SPI123SEL_PLL2_P_CK
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#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
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#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
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#define STM32_CECSEL STM32_CECSEL_LSE_CK
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#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
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#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1
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#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
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#define STM32_USART16SEL STM32_USART16SEL_PLL2_Q_CK
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#define STM32_USART234578SEL STM32_USART234578SEL_PLL2_Q_CK
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#define STM32_SPI6SEL STM32_SPI6SEL_PLL2_Q_CK
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#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
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#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
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#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK
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#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
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#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
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#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_OTG1 TRUE
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#define STM32_USB_USE_OTG2 FALSE
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#define STM32_USB_OTG1_RX_FIFO_SIZE 512
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#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
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#define STM32_USB_HOST_WAKEUP_DURATION 2
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