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hal_flash_device.h
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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file hal_flash_device.h
19 * @brief Winbond W25Q serial flash driver header.
20 *
21 * @addtogroup WINBONT_N25Q
22 * @{
23 */
24
25#ifndef HAL_FLASH_DEVICE_H
26#define HAL_FLASH_DEVICE_H
27
28/*===========================================================================*/
29/* Driver constants. */
30/*===========================================================================*/
31
32/**
33 * @name Device capabilities
34 * @{
35 */
36#define SNOR_DEVICE_SUPPORTS_XIP TRUE
37/** @} */
38
39/**
40 * @name Device identification
41 * @{
42 */
43#define W25Q_SUPPORTED_MANUFACTURE_IDS {0xEF}
44#define W25Q_SUPPORTED_MEMORY_TYPE_IDS {0x40, 0x60}
45/** @} */
46
47/**
48 * @name Command codes
49 * @{
50 */
51#define W25Q_CMD_RESET_ENABLE 0x66
52#define W25Q_CMD_RESET 0x99
53#define W25Q_CMD_READ_JEDEC_ID 0x9F
54#define W25Q_CMD_READ_SFDP_REGISTER 0x5A
55#define W25Q_CMD_READ 0x03
56#define W25Q_CMD_FAST_READ 0x0B
57#define W25Q_CMD_WRITE_ENABLE 0x06
58#define W25Q_CMD_WRITE_DISABLE 0x04
59#define W25Q_CMD_READ_STATUS_REGISTER 0x05
60#define W25Q_CMD_WRITE_STATUS_REGISTER 0x01
61#define W25Q_CMD_PAGE_PROGRAM 0x02
62#define W25Q_CMD_SECTOR_ERASE 0x20
63#define W25Q_CMD_32K_BLOCK_ERASE 0x53
64#define W25Q_CMD_64K_BLOCK_ERASE 0xD8
65#define W25Q_CMD_BULK_ERASE 0xC7
66#define W25Q_CMD_PROGRAM_ERASE_RESUME 0x7A
67#define W25Q_CMD_PROGRAM_ERASE_SUSPEND 0x75
68#define W25Q_CMD_READ_UID_ARRAY 0x4B
69#define W25Q_CMD_PROGRAM_SECURITY_REGS 0x42
70/** @} */
71
72/**
73 * @name Flags status register bits
74 * @{
75 */
76#define W25Q_FLAGS_BUSY 0x01U
77/** @} */
78
79/**
80 * @name Bus interface modes.
81 * @{
82 */
83#define W25Q_BUS_MODE_WSPI1L 1U
84#define W25Q_BUS_MODE_WSPI2L 2U
85#define W25Q_BUS_MODE_WSPI4L 4U
86/** @} */
87
88/*===========================================================================*/
89/* Driver pre-compile time settings. */
90/*===========================================================================*/
91
92/**
93 * @brief Switch WSPI bus width on initialization.
94 * @details A bus width initialization is performed by writing the
95 * Enhanced Volatile Configuration Register. If the flash
96 * device is configured using the Non Volatile Configuration
97 * Register then this option is not required.
98 * @note This option is only valid in WSPI bus mode.
99 */
100#if !defined(W25Q_SWITCH_WIDTH) || defined(__DOXYGEN__)
101#define W25Q_SWITCH_WIDTH TRUE
102#endif
103
104/**
105 * @brief Device bus mode to be used.
106 * #note if @p W25Q_SWITCH_WIDTH is @p FALSE then this is the bus mode
107 * that the device is expected to be using.
108 * #note if @p W25Q_SWITCH_WIDTH is @p TRUE then this is the bus mode
109 * that the device will be switched in.
110 * @note This option is only valid in WSPI bus mode.
111 */
112#if !defined(W25Q_BUS_MODE) || defined(__DOXYGEN__)
113#define W25Q_BUS_MODE W25Q_BUS_MODE_WSPI4L
114#endif
115
116/**
117 * @brief Delays insertions.
118 * @details If enabled this options inserts delays into the flash waiting
119 * routines releasing some extra CPU time for threads with lower
120 * priority, this may slow down the driver a bit however.
121 */
122#if !defined(W25Q_NICE_WAITING) || defined(__DOXYGEN__)
123#define W25Q_NICE_WAITING TRUE
124#endif
125
126/**
127 * @brief Uses 4kB sub-sectors rather than 64kB sectors.
128 */
129#if !defined(W25Q_USE_SUB_SECTORS) || defined(__DOXYGEN__)
130#define W25Q_USE_SUB_SECTORS TRUE
131#endif
132
133/**
134 * @brief Size of the compare buffer.
135 * @details This buffer is allocated in the stack frame of the function
136 * @p flashVerifyErase() and its size must be a power of two.
137 * Larger buffers lead to better verify performance but increase
138 * stack usage for that function.
139 */
140#if !defined(W25Q_COMPARE_BUFFER_SIZE) || defined(__DOXYGEN__)
141#define W25Q_COMPARE_BUFFER_SIZE 32
142#endif
143
144/**
145 * @brief Number of dummy cycles for fast read (1..15).
146 * @details This is the number of dummy cycles to be used for fast read
147 * operations.
148 */
149#if !defined(W25Q_READ_DUMMY_CYCLES) || defined(__DOXYGEN__)
150#define W25Q_READ_DUMMY_CYCLES 1
151#endif
152
153/*===========================================================================*/
154/* Derived constants and error checks. */
155/*===========================================================================*/
156
157#if (W25Q_COMPARE_BUFFER_SIZE & (W25Q_COMPARE_BUFFER_SIZE - 1)) != 0
158#error "invalid W25Q_COMPARE_BUFFER_SIZE value"
159#endif
160
161#if (W25Q_READ_DUMMY_CYCLES < 1) || (W25Q_READ_DUMMY_CYCLES > 15)
162#error "invalid W25Q_READ_DUMMY_CYCLES value (1..15)"
163#endif
164
165#if (W25Q_BUS_MODE == W25Q_BUS_MODE_WSPI4L) || defined(__DOXYGEN__)
166/**
167 * @brief WSPI settings for command only.
168 */
169#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_FOUR_LINES | \
170 WSPI_CFG_ADDR_MODE_NONE | \
171 WSPI_CFG_ALT_MODE_NONE | \
172 WSPI_CFG_DATA_MODE_NONE | \
173 WSPI_CFG_CMD_SIZE_8 | \
174 WSPI_CFG_ADDR_SIZE_24)
175
176/**
177 * @brief WSPI settings for command and address.
178 */
179#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_FOUR_LINES | \
180 WSPI_CFG_ADDR_MODE_FOUR_LINES | \
181 WSPI_CFG_ALT_MODE_NONE | \
182 WSPI_CFG_DATA_MODE_NONE | \
183 WSPI_CFG_CMD_SIZE_8 | \
184 WSPI_CFG_ADDR_SIZE_24)
185
186/**
187 * @brief WSPI settings for command and data.
188 */
189#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \
190 WSPI_CFG_ADDR_MODE_NONE | \
191 WSPI_CFG_ALT_MODE_NONE | \
192 WSPI_CFG_DATA_MODE_FOUR_LINES | \
193 WSPI_CFG_CMD_SIZE_8 | \
194 WSPI_CFG_ADDR_SIZE_24)
195
196/**
197 * @brief WSPI settings for command, address and data.
198 */
199#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_FOUR_LINES | \
200 WSPI_CFG_ADDR_MODE_FOUR_LINES | \
201 WSPI_CFG_ALT_MODE_NONE | \
202 WSPI_CFG_DATA_MODE_FOUR_LINES | \
203 WSPI_CFG_CMD_SIZE_8 | \
204 WSPI_CFG_ADDR_SIZE_24)
205
206#elif W25Q_BUS_MODE == W25Q_BUS_MODE_WSPI2L
207#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_TWO_LINES | \
208 WSPI_CFG_ADDR_MODE_NONE | \
209 WSPI_CFG_ALT_MODE_NONE | \
210 WSPI_CFG_DATA_MODE_NONE | \
211 WSPI_CFG_CMD_SIZE_8 | \
212 WSPI_CFG_ADDR_SIZE_24)
213
214#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_TWO_LINES | \
215 WSPI_CFG_ADDR_MODE_TWO_LINES | \
216 WSPI_CFG_ALT_MODE_NONE | \
217 WSPI_CFG_DATA_MODE_NONE | \
218 WSPI_CFG_CMD_SIZE_8 | \
219 WSPI_CFG_ADDR_SIZE_24)
220
221#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_TWO_LINES | \
222 WSPI_CFG_ADDR_MODE_NONE | \
223 WSPI_CFG_ALT_MODE_NONE | \
224 WSPI_CFG_DATA_MODE_TWO_LINES | \
225 WSPI_CFG_CMD_SIZE_8 | \
226 WSPI_CFG_ADDR_SIZE_24)
227
228#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
229 WSPI_CFG_ADDR_MODE_ONE_LINE | \
230 WSPI_CFG_ALT_MODE_NONE | \
231 WSPI_CFG_DATA_MODE_ONE_LINE | \
232 WSPI_CFG_CMD_SIZE_8 | \
233 WSPI_CFG_ADDR_SIZE_24)
234
235#elif W25Q_BUS_MODE == W25Q_BUS_MODE_WSPI1L
236#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_ONE_LINE | \
237 WSPI_CFG_ADDR_MODE_NONE | \
238 WSPI_CFG_ALT_MODE_NONE | \
239 WSPI_CFG_DATA_MODE_NONE | \
240 WSPI_CFG_CMD_SIZE_8 | \
241 WSPI_CFG_ADDR_SIZE_24)
242
243#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_ONE_LINE | \
244 WSPI_CFG_ADDR_MODE_ONE_LINE | \
245 WSPI_CFG_ALT_MODE_NONE | \
246 WSPI_CFG_DATA_MODE_NONE | \
247 WSPI_CFG_CMD_SIZE_8 | \
248 WSPI_CFG_ADDR_SIZE_24)
249
250#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
251 WSPI_CFG_ADDR_MODE_NONE | \
252 WSPI_CFG_ALT_MODE_NONE | \
253 WSPI_CFG_DATA_MODE_ONE_LINE | \
254 WSPI_CFG_CMD_SIZE_8 | \
255 WSPI_CFG_ADDR_SIZE_24)
256
257#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
258 WSPI_CFG_ADDR_MODE_ONE_LINE | \
259 WSPI_CFG_ALT_MODE_NONE | \
260 WSPI_CFG_DATA_MODE_ONE_LINE | \
261 WSPI_CFG_CMD_SIZE_8 | \
262 WSPI_CFG_ADDR_SIZE_24)
263
264#else
265#error "invalid W25Q_BUS_MODE setting"
266#endif
267
268/*===========================================================================*/
269/* Driver data structures and types. */
270/*===========================================================================*/
271
272/*===========================================================================*/
273/* Driver macros. */
274/*===========================================================================*/
275
276/*===========================================================================*/
277/* External declarations. */
278/*===========================================================================*/
279
280#if !defined(__DOXYGEN__)
281extern flash_descriptor_t snor_descriptor;
282#endif
283
284#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && (WSPI_SUPPORTS_MEMMAP == TRUE)
285extern const wspi_command_t snor_memmap_read;
286#endif
287
288#ifdef __cplusplus
289extern "C" {
290#endif
291 void snor_device_init(SNORDriver *devp);
292 flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset,
293 size_t n, uint8_t *rp);
294 flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset,
295 size_t n, const uint8_t *pp);
296 flash_error_t snor_device_start_erase_all(SNORDriver *devp);
297 flash_error_t snor_device_start_erase_sector(SNORDriver *devp,
298 flash_sector_t sector);
299 flash_error_t snor_device_verify_erase(SNORDriver *devp,
300 flash_sector_t sector);
301 flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec);
302 flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset,
303 size_t n, uint8_t *rp);
304#if (SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI) && \
305 (SNOR_DEVICE_SUPPORTS_XIP == TRUE)
306 void snor_activate_xip(SNORDriver *devp);
307 void snor_reset_xip(SNORDriver *devp);
308#endif
309#ifdef __cplusplus
310}
311#endif
312
313#endif /* HAL_FLASH_DEVICE_H */
314
315/** @} */
316
snor_activate_xip
void snor_activate_xip(SNORDriver *devp)
Definition hal_flash_device.c:581
snor_device_verify_erase
flash_error_t snor_device_verify_erase(SNORDriver *devp, flash_sector_t sector)
Definition hal_flash_device.c:489
snor_device_query_erase
flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec)
Definition hal_flash_device.c:524
snor_device_read_sfdp
flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, size_t n, uint8_t *rp)
Definition hal_flash_device.c:546
snor_reset_xip
void snor_reset_xip(SNORDriver *devp)
Definition hal_flash_device.c:595
snor_device_start_erase_sector
flash_error_t snor_device_start_erase_sector(SNORDriver *devp, flash_sector_t sector)
Definition hal_flash_device.c:475
snor_memmap_read
const wspi_command_t snor_memmap_read
Fast read command for memory mapped mode.
Definition hal_flash_device.c:56
snor_device_read
flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, size_t n, uint8_t *rp)
Definition hal_flash_device.c:409
snor_device_program
flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, size_t n, const uint8_t *pp)
Definition hal_flash_device.c:428
snor_descriptor
flash_descriptor_t snor_descriptor
Flash descriptor.
Definition hal_flash_device.c:39
snor_device_init
void snor_device_init(SNORDriver *devp)
Definition hal_flash_device.c:264
snor_device_start_erase_all
flash_error_t snor_device_start_erase_all(SNORDriver *devp)
Definition hal_flash_device.c:464
offset
uint16_t offset
Definition tunerstudio.h:0
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