Injection timing using FPGA for Common Rail Diesel

Hardware inside and outside of the ECU
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jwm
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Injection timing using FPGA for Common Rail Diesel

Post by jwm »

Hi,

I'm new to this forum. I have been tossing the idea to run a V6 Mercedes Benz common rail Diesel off of an aftermarket ECU for some time and studied a lot of literature. I have looked at some commercial solutions but they are mostly very expensive and it is a bit of a gamble to throw $4k at a small box to find out it is not optimal. I would also like to have more freedom to experiment and learn. At this moment only Adaptronic 1280 falls into this category. I like the rusEFI approach better because of its open source approach and the community (albeit seemingly small) behind it.

One of the differences of a modern diesel is that the injection timing is more complex. Timing should be very precise and multiple 100-300µs bursts are required for a smooth operation and emission reduction.

The idea I had is to develop an FPGA design that would take most of the stress out of the main CPU. The crank and cam signals would drive this digital timer as well as a number of writable registers that would dictate fuel quantity (=duration of the injection pulses) that is also depending on rail pressure, fuel temperature, atmospheric pressure, torque demand and other parameters.

Anyone interested to discuss this topic further on this board?

Thanks,

JW
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kb1gtt
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Re: Injection timing using FPGA for Common Rail Diesel

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Yes interested. I even once made a QUCS simulation which could potentially drive the high voltage of these injectors. However in modern days the chips to drive them have become much more available. There was another person here who recently seemed interested, but as commonly happens, they went silent. Perhaps got distracted with another project.

Any how I've been tempted to make a kind of add-on board such that we could physically drive these high pressure injectors. I believe the STM32 is fast enough for driving these kinds of injectors. In the rusEFI software, it uses the STM32's hardware timers. The software does maintenance operations, and the timer does the timing critical stuff. I seem to recall the latency or low lever jitter of this timer is around 1uS, and the firmware tick is around 1mS. While a FPGA can get to a latency of around 5nS, the 1uS is probably good enough for direct injection needs. As well if we need lower jitter, there are chips which we can port to that offer TPU's. Those TPU's have latency's around 7nS to 10nS. So I don't see any real value in an FPGA. I do see an FPGA as being complicated and hard to develop with.

See this thread for some more common rail information.
http://rusefi.com/forum/viewtopic.php?f=3&t=1246
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Re: Injection timing using FPGA for Common Rail Diesel

Post by AndreyB »

FPGA is maybe a solution for precise signal genefation, but probably not the most obvious one.

I'd say that before we go FPGA we need to figure out where is thr limit of stm32f4 in this regard which would need some effort from software developers.
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jwm
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Re: Injection timing using FPGA for Common Rail Diesel

Post by jwm »

I have to admit that the CPU in the original common rail Bosch ECU is probably less capable than the STM32F4. It is a RISC chip with 64bit FPU running at 40MHz only. A lot will depend on how clever the timer architecture is set up of each CPU design.

If you can create cam/crank synchronized pulses at will at 1µs jitter accuracy then I guess you do not need a FPGA but you might need a lot of time getting things right, especially when an RTOS is involved (and all timer related activity has to run as ISR to take priority over the scheduler).

At the moment I do not know a lot on how the rusEFI system is dealing with timing and how the STM32F4 timers are used to get at 1µs jitter values. Before delving into this subject deeper I will have to study the source code and documentation a little more and read some more posts on this forum.

Cheers,

JW
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mobyfab
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Re: Injection timing using FPGA for Common Rail Diesel

Post by mobyfab »

Another good reason to use hardware timers for signals, as I advised :)
Right now the signals are triggered via software from a timer interrupt, which is not as precise. (but you get more outputs and flexibility)

You can do that with a general purpose MCU, 1us resolution is easy to achieve with a 32b timer running a 1Mhz.
In theory you can go down to 23.8ns on the F405 when you run the timer at it's max frequency of 42Mhz.

There's even a 217ps timer on the STM32F334 but that would be overkill.
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Re: Injection timing using FPGA for Common Rail Diesel

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jwm wrote:I will have to study the source code and documentation
If you find some documentation let us know. We are a bit weak in the documentation department, so I joke that it does not exist. There are many note and helpful information in the source code.

I may be wrong with my overly simplified version of this, but at the core, it uses a timer which triggers ISR events. ISR events are commonly ignition, fuel pulses, etc. These events get bumped up in priority when ever the timer ISR hits a timing critical event. AKA you have some lag as you jump through index tables and have some additional logic between the toggling an output bit. This is where the current aprox 1uS timer jitter comes from. It could probably be reduced if wrote some ASM code, or as mobyfab mentions, if we switch to pure hardware timer. AKA bits toggle directly from the timer and not ISR code execution.

At the moment I think the timer jitter would be able to preform fairly well, but to there is room for better performance. I think the real problem is the lack of electrical hardware, and the lack of people who have engines which they can experiment with. I can help with the electrical hardware, but a person who knows how this works and can get the software bits done is a different situation.
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Re: Injection timing using FPGA for Common Rail Diesel

Post by Rhinoman »

mobyfab wrote: You can do that with a general purpose MCU, 1us resolution is easy to achieve with a 32b timer running a 1Mhz.
In theory you can go down to 23.8ns on the F405 when you run the timer at it's max frequency of 42Mhz.
Yes my 1991 ECU achieves 1us resolution running a 6801 variant with a 1 MHz E clock driving a 16-bit timer. I think the software controlled timer comes from MS which copied an ancient 1980s system that used a microprocessor rather than a microcontroller.
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Re: Injection timing using FPGA for Common Rail Diesel

Post by AndreyB »

Rhinoman wrote:I think the software controlled timer comes from MS which copied an ancient 1980s system that used a microprocessor rather than a microcontroller.
comes from MS into where?
Obviously nothing comes into rusEfi from MS, just wanted to reiterate this since your opinion is simply not based on much.
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Re: Injection timing using FPGA for Common Rail Diesel

Post by kb1gtt »

I'm not sure how MS similarities is applicable to common rail. Perhaps that conversation is best migrated to another thread. I have not looked at MS code for about 15 years, but from what I recall they had very core differences. In rusEFI, it uses an OS and hardware timer, while MS used a complicated ISR index table logic which consumes stack memory. Both are very different toplogies, but both eventually toggle a pin which fires the injector. So there are similarities as both toggle a pin, but not much beyond that.

About common rail.... the key thing to take from this, is that the current design is probably accurate enough for many common rail setups. However it may need some optimization for higher RPM, and optimization for fine tuning high horse power applications. As it stands now the topology should be accurate enough to start an engine and to make use of like 80% of the engines capabilities. However getting the remaining 20% out of the engines potential performance, would require some significant optimization in the scheduler. It can be physically done, it just requires software resources which are in short supply. I can't speak for @ but I would bet if we had an engine which was started and running, I would bet the software resources would become available. Right now a key problem we have is that we don't have hardware to work with, which makes the software development very difficult and time consuming. This extra work causes other tasks to get prioritized before tasks like further optimizing the event scheduler.
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Re: Injection timing using FPGA for Common Rail Diesel

Post by kb1gtt »

I see the 30591 Bosch is a commonly available chip in many sources like eBay and aliexpress. Does anyone know of a datasheet for this chip? Does it include the high side and low side drive, or is it just a driver? Does it include the voltage boost stuff? Etc.

Is there a particular chip we should make a break out board for? I'm a bit concerned that the MC33816 seems to have many IO and many complications. I suspect that there are chips which can minimize the complication. Basically SPI for some configuration and diagnostics, then from the MCU standpoint, it's just MCU pin to fire the injector. Are there any chips which are like that, or should we some how make a break out board which does this?
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