Clock

Files
file	fsl_clock.h

Data Structures
struct	_scg_sys_clk_config
	SCG system clock configuration. More...
struct	_scg_sosc_config
	SCG system OSC configuration. More...
struct	_scg_sirc_config
	SCG slow IRC clock configuration. More...
struct	_scg_firc_trim_config
	SCG fast IRC clock trim configuration. More...
struct	_scg_firc_config_t
	SCG fast IRC clock configuration. More...
struct	_scg_spll_config
	SCG system PLL configuration. More...

Variables
uint32_t	_scg_sys_clk_config::divSlow: 4
uint32_t	_scg_sys_clk_config::divBus: 4
uint32_t	: 4
uint32_t	: 4
uint32_t	_scg_sys_clk_config::divCore: 4
uint32_t	: 4
uint32_t	_scg_sys_clk_config::src: 4
uint32_t	: 4
uint32_t	_scg_sosc_config::freq
scg_sosc_monitor_mode_t	_scg_sosc_config::monitorMode
uint8_t	_scg_sosc_config::enableMode
scg_async_clk_div_t	_scg_sosc_config::div1
scg_async_clk_div_t	_scg_sosc_config::div2
scg_sosc_mode_t	_scg_sosc_config::workMode
uint32_t	_scg_sirc_config::enableMode
scg_async_clk_div_t	_scg_sirc_config::div1
scg_async_clk_div_t	_scg_sirc_config::div2
scg_sirc_range_t	_scg_sirc_config::range
scg_firc_trim_mode_t	_scg_firc_trim_config::trimMode
scg_firc_trim_src_t	_scg_firc_trim_config::trimSrc
scg_firc_trim_div_t	_scg_firc_trim_config::trimDiv
uint8_t	_scg_firc_trim_config::trimCoar
uint8_t	_scg_firc_trim_config::trimFine
uint32_t	_scg_firc_config_t::enableMode
scg_async_clk_div_t	_scg_firc_config_t::div1
scg_async_clk_div_t	_scg_firc_config_t::div2
scg_firc_range_t	_scg_firc_config_t::range
const scg_firc_trim_config_t *	_scg_firc_config_t::trimConfig
uint8_t	_scg_spll_config::enableMode
scg_spll_monitor_mode_t	_scg_spll_config::monitorMode
scg_async_clk_div_t	_scg_spll_config::div1
scg_async_clk_div_t	_scg_spll_config::div2
scg_spll_src_t	_scg_spll_config::src
uint8_t	_scg_spll_config::prediv
uint8_t	_scg_spll_config::mult

Driver version
enum	_clock_name {   kCLOCK_CoreSysClk , kCLOCK_BusClk , kCLOCK_FlexBusClk , kCLOCK_FlashClk ,   kCLOCK_ScgSysOscClk , kCLOCK_ScgSircClk , kCLOCK_ScgFircClk , kCLOCK_ScgSysPllClk ,   kCLOCK_ScgSysOscAsyncDiv1Clk , kCLOCK_ScgSysOscAsyncDiv2Clk , kCLOCK_ScgSircAsyncDiv1Clk , kCLOCK_ScgSircAsyncDiv2Clk ,   kCLOCK_ScgFircAsyncDiv1Clk , kCLOCK_ScgFircAsyncDiv2Clk , kCLOCK_ScgSysPllAsyncDiv1Clk , kCLOCK_ScgSysPllAsyncDiv2Clk ,   kCLOCK_LpoClk , kCLOCK_Osc32kClk , kCLOCK_ErClk }
	Clock name used to get clock frequency. More...
enum	_clock_ip_src {   kCLOCK_IpSrcNoneOrExt = 0U , kCLOCK_IpSrcSysOscAsync = 1U , kCLOCK_IpSrcSircAsync = 2U , kCLOCK_IpSrcFircAsync = 3U ,   kCLOCK_IpSrcSysPllAsync = 6U }
	Clock source for peripherals that support various clock selections. More...
enum	_clock_ip_name {   kCLOCK_IpInvalid = 0U , kCLOCK_Dma0 = 0x40065020U , kCLOCK_Sysmpu0 = 0x40065034U , kCLOCK_Flash0 = 0x40065080U ,   kCLOCK_Dmamux0 = 0x40065084U , kCLOCK_Flexcan0 = 0x40065090U , kCLOCK_Flexcan1 = 0x40065094U , kCLOCK_Ftm3 = 0x40065098U ,   kCLOCK_Adc1 = 0x4006509CU , kCLOCK_Lpspi0 = 0x400650B0U , kCLOCK_Lpspi1 = 0x400650B4U , kCLOCK_Pdb1 = 0x400650C4U ,   kCLOCK_Crc0 = 0x400650C8U , kCLOCK_Pdb2 = 0x400650CCU , kCLOCK_Pdb0 = 0x400650D8U , kCLOCK_Lpit0 = 0x400650DCU ,   kCLOCK_Ftm0 = 0x400650E0U , kCLOCK_Ftm1 = 0x400650E4U , kCLOCK_Ftm2 = 0x400650E8U , kCLOCK_Adc0 = 0x400650ECU ,   kCLOCK_Adc2 = 0x400650F0U , kCLOCK_Rtc0 = 0x400650F4U , kCLOCK_Dac0 = 0x400650FCU , kCLOCK_Lptmr0 = 0x40065100U ,   kCLOCK_PortA = 0x40065124U , kCLOCK_PortB = 0x40065128U , kCLOCK_PortC = 0x4006512CU , kCLOCK_PortD = 0x40065130U ,   kCLOCK_PortE = 0x40065134U , kCLOCK_Pwt0 = 0x40065158U , kCLOCK_Flexio0 = 0x40065168U , kCLOCK_RtcOsc0 = 0x40065180U ,   kCLOCK_Ewm0 = 0x40065184U , kCLOCK_Lpi2c0 = 0x40065198U , kCLOCK_Lpi2c1 = 0x4006519CU , kCLOCK_Lpuart0 = 0x400651A8U ,   kCLOCK_Lpuart1 = 0x400651ACU , kCLOCK_Lpuart2 = 0x400651B0U , kCLOCK_Cmp0 = 0x400651CCU , kCLOCK_Cmp1 = 0x400651D0U ,   kCLOCK_Cmp2 = 0x400651D4U }
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. It is defined as the corresponding register address. More...
enum	_osc32_mode { kOSC32_Bypass = OSC32_CR_ROSCEN_MASK , kOSC32_Crystal = OSC32_CR_ROSCEN_MASK | OSC32_CR_ROSCEREFS_MASK , kOSC32_CrystalEnableInStop }
	OSC32 work mode. More...
enum	_scg_status { kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1) , kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) }
	SCG status return codes. More...
enum	_scg_sys_clk { kSCG_SysClkSlow , kSCG_SysClkBus , kSCG_SysClkCore }
	SCG system clock type. More...
enum	_scg_sys_clk_src { kSCG_SysClkSrcSysOsc = 1U , kSCG_SysClkSrcSirc = 2U , kSCG_SysClkSrcFirc = 3U , kSCG_SysClkSrcSysPll = 6U }
	SCG system clock source. More...
enum	_scg_sys_clk_div {   kSCG_SysClkDivBy1 = 0U , kSCG_SysClkDivBy2 = 1U , kSCG_SysClkDivBy3 = 2U , kSCG_SysClkDivBy4 = 3U ,   kSCG_SysClkDivBy5 = 4U , kSCG_SysClkDivBy6 = 5U , kSCG_SysClkDivBy7 = 6U , kSCG_SysClkDivBy8 = 7U ,   kSCG_SysClkDivBy9 = 8U , kSCG_SysClkDivBy10 = 9U , kSCG_SysClkDivBy11 = 10U , kSCG_SysClkDivBy12 = 11U ,   kSCG_SysClkDivBy13 = 12U , kSCG_SysClkDivBy14 = 13U , kSCG_SysClkDivBy15 = 14U , kSCG_SysClkDivBy16 = 15U }
	SCG system clock divider value. More...
enum	_clock_clkout_src {   kClockClkoutSelScgSlow = 0U , kClockClkoutSelSysOsc = 1U , kClockClkoutSelSirc = 2U , kClockClkoutSelFirc = 3U ,   kClockClkoutSelSysPll = 6U }
	SCG clock out configuration (CLKOUTSEL). More...
enum	_scg_async_clk { kSCG_AsyncDiv1Clk , kSCG_AsyncDiv2Clk }
	SCG asynchronous clock type. More...
enum	scg_async_clk_div {   kSCG_AsyncClkDisable = 0U , kSCG_AsyncClkDivBy1 = 1U , kSCG_AsyncClkDivBy2 = 2U , kSCG_AsyncClkDivBy4 = 3U ,   kSCG_AsyncClkDivBy8 = 4U , kSCG_AsyncClkDivBy16 = 5U , kSCG_AsyncClkDivBy32 = 6U , kSCG_AsyncClkDivBy64 = 7U }
	SCG asynchronous clock divider value. More...
enum	_scg_sosc_monitor_mode { kSCG_SysOscMonitorDisable = 0U , kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK , kSCG_SysOscMonitorReset }
	SCG system OSC monitor mode. More...
enum	_scg_sosc_mode { kSCG_SysOscModeExt = 0U , kSCG_SysOscModeOscLowPower = SCG_SOSCCFG_EREFS_MASK , kSCG_SysOscModeOscHighGain = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_HGO_MASK }
	OSC work mode. More...
enum	_scg_sosc_enable_mode { kSCG_SysOscEnable = SCG_SOSCCSR_SOSCEN_MASK , kSCG_SysOscEnableInStop = SCG_SOSCCSR_SOSCSTEN_MASK , kSCG_SysOscEnableInLowPower = SCG_SOSCCSR_SOSCLPEN_MASK , kSCG_SysOscEnableErClk = SCG_SOSCCSR_SOSCERCLKEN_MASK }
	OSC enable mode. More...
enum	_scg_sirc_range { kSCG_SircRangeLow , kSCG_SircRangeHigh }
	SCG slow IRC clock frequency range. More...
enum	_scg_sirc_enable_mode { kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK , kSCG_SircEnableInStop = SCG_SIRCCSR_SIRCSTEN_MASK , kSCG_SircEnableInLowPower = SCG_SIRCCSR_SIRCLPEN_MASK }
	SIRC enable mode. More...
enum	_scg_firc_trim_mode { kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK , kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK }
	SCG fast IRC trim mode. More...
enum	_scg_firc_trim_div {   kSCG_FircTrimDivBy1 , kSCG_FircTrimDivBy128 , kSCG_FircTrimDivBy256 , kSCG_FircTrimDivBy512 ,   kSCG_FircTrimDivBy1024 , kSCG_FircTrimDivBy2048 }
	SCG fast IRC trim predivided value for system OSC. More...
enum	_scg_firc_trim_src { kSCG_FircTrimSrcSysOsc = 2U }
	SCG fast IRC trim source. More...
enum	_scg_firc_range { kSCG_FircRange48M , kSCG_FircRange52M , kSCG_FircRange56M , kSCG_FircRange60M }
	SCG fast IRC clock frequency range. More...
enum	_scg_firc_enable_mode { kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK , kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK , kSCG_FircEnableInLowPower = SCG_FIRCCSR_FIRCLPEN_MASK , kSCG_FircDisableRegulator = SCG_FIRCCSR_FIRCREGOFF_MASK }
	FIRC enable mode. More...
enum	_scg_spll_src { kSCG_SysPllSrcSysOsc , kSCG_SysPllSrcFirc }
	SCG system PLL clock source. More...
enum	_scg_spll_monitor_mode { kSCG_SysPllMonitorDisable = 0U , kSCG_SysPllMonitorInt = SCG_SPLLCSR_SPLLCM_MASK , kSCG_SysPllMonitorReset }
	SCG system PLL monitor mode. More...
enum	_scg_spll_enable_mode { kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK , kSCG_SysPllEnableInStop = SCG_SPLLCSR_SPLLSTEN_MASK }
	SPLL enable mode. More...
typedef enum _clock_name	clock_name_t
	Clock name used to get clock frequency.
typedef enum _clock_ip_src	clock_ip_src_t
	Clock source for peripherals that support various clock selections.
typedef enum _clock_ip_name	clock_ip_name_t
	Peripheral clock name difinition used for clock gate, clock source and clock divider setting. It is defined as the corresponding register address.
typedef enum _osc32_mode	osc32_mode_t
	OSC32 work mode.
typedef enum _scg_sys_clk	scg_sys_clk_t
	SCG system clock type.
typedef enum _scg_sys_clk_src	scg_sys_clk_src_t
	SCG system clock source.
typedef enum _scg_sys_clk_div	scg_sys_clk_div_t
	SCG system clock divider value.
typedef struct _scg_sys_clk_config	scg_sys_clk_config_t
	SCG system clock configuration.
typedef enum _clock_clkout_src	clock_clkout_src_t
	SCG clock out configuration (CLKOUTSEL).
typedef enum _scg_async_clk	scg_async_clk_t
	SCG asynchronous clock type.
typedef enum scg_async_clk_div	scg_async_clk_div_t
	SCG asynchronous clock divider value.
typedef enum _scg_sosc_monitor_mode	scg_sosc_monitor_mode_t
	SCG system OSC monitor mode.
typedef enum _scg_sosc_mode	scg_sosc_mode_t
	OSC work mode.
typedef struct _scg_sosc_config	scg_sosc_config_t
	SCG system OSC configuration.
typedef enum _scg_sirc_range	scg_sirc_range_t
	SCG slow IRC clock frequency range.
typedef struct _scg_sirc_config	scg_sirc_config_t
	SCG slow IRC clock configuration.
typedef enum _scg_firc_trim_mode	scg_firc_trim_mode_t
	SCG fast IRC trim mode.
typedef enum _scg_firc_trim_div	scg_firc_trim_div_t
	SCG fast IRC trim predivided value for system OSC.
typedef enum _scg_firc_trim_src	scg_firc_trim_src_t
	SCG fast IRC trim source.
typedef struct _scg_firc_trim_config	scg_firc_trim_config_t
	SCG fast IRC clock trim configuration.
typedef enum _scg_firc_range	scg_firc_range_t
	SCG fast IRC clock frequency range.
typedef struct _scg_firc_config_t	scg_firc_config_t
	SCG fast IRC clock configuration.
typedef enum _scg_spll_src	scg_spll_src_t
	SCG system PLL clock source.
typedef enum _scg_spll_monitor_mode	scg_spll_monitor_mode_t
	SCG system PLL monitor mode.
typedef struct _scg_spll_config	scg_spll_config_t
	SCG system PLL configuration.
volatile uint32_t	g_xtal0Freq
	External XTAL0 (OSC0/SYSOSC) clock frequency.
volatile uint32_t	g_xtal32Freq
	External XTAL32/EXTAL32 clock frequency.
static void	CLOCK_EnableClock (clock_ip_name_t name)
	Enable the clock for specific IP.
static void	CLOCK_DisableClock (clock_ip_name_t name)
	Disable the clock for specific IP.
static bool	CLOCK_IsEnabledByOtherCore (clock_ip_name_t name)
	Check whether the clock is already enabled and configured by any other core.
static void	CLOCK_SetIpSrc (clock_ip_name_t name, clock_ip_src_t src)
	Set the clock source for specific IP module.
uint32_t	CLOCK_GetFreq (clock_name_t clockName)
	Gets the clock frequency for a specific clock name.
uint32_t	CLOCK_GetCoreSysClkFreq (void)
	Get the core clock or system clock frequency.
uint32_t	CLOCK_GetBusClkFreq (void)
	Get the bus clock frequency.
uint32_t	CLOCK_GetFlashClkFreq (void)
	Get the flash clock frequency.
uint32_t	CLOCK_GetOsc32kClkFreq (void)
	Get the OSC 32K clock frequency (OSC32KCLK).
uint32_t	CLOCK_GetErClkFreq (void)
	Get the external reference clock frequency (ERCLK).
uint32_t	CLOCK_GetIpFreq (clock_ip_name_t name)
	Gets the clock frequency for a specific IP module.

MCU System Clock.
uint32_t	CLOCK_GetSysClkFreq (scg_sys_clk_t type)
	Gets the SCG system clock frequency.
static void	CLOCK_SetVlprModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for VLPR mode.
static void	CLOCK_SetRunModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for RUN mode.
static void	CLOCK_SetHsrunModeSysClkConfig (const scg_sys_clk_config_t *config)
	Sets the system clock configuration for HSRUN mode.
static void	CLOCK_GetCurSysClkConfig (scg_sys_clk_config_t *config)
	Gets the system clock configuration in the current power mode.
static void	CLOCK_SetClkOutSel (clock_clkout_src_t setting)
	Sets the clock out selection.

SCG System OSC Clock.
status_t	CLOCK_InitSysOsc (const scg_sosc_config_t *config)
	Initializes the SCG system OSC.
status_t	CLOCK_DeinitSysOsc (void)
	De-initializes the SCG system OSC.
static void	CLOCK_SetSysOscAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider.
uint32_t	CLOCK_GetSysOscFreq (void)
	Gets the SCG system OSC clock frequency (SYSOSC).
uint32_t	CLOCK_GetSysOscAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the system OSC.
static bool	CLOCK_IsSysOscErr (void)
	Checks whether the system OSC clock error occurs.
static void	CLOCK_ClearSysOscErr (void)
	Clears the system OSC clock error.
static void	CLOCK_SetSysOscMonitorMode (scg_sosc_monitor_mode_t mode)
	Sets the system OSC monitor mode.
static bool	CLOCK_IsSysOscValid (void)
	Checks whether the system OSC clock is valid.

SCG Slow IRC Clock.
status_t	CLOCK_InitSirc (const scg_sirc_config_t *config)
	Initializes the SCG slow IRC clock.
status_t	CLOCK_DeinitSirc (void)
	De-initializes the SCG slow IRC.
static void	CLOCK_SetSircAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider.
uint32_t	CLOCK_GetSircFreq (void)
	Gets the SCG SIRC clock frequency.
uint32_t	CLOCK_GetSircAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the SIRC.
static bool	CLOCK_IsSircValid (void)
	Checks whether the SIRC clock is valid.

SCG Fast IRC Clock.
status_t	CLOCK_InitFirc (const scg_firc_config_t *config)
	Initializes the SCG fast IRC clock.
status_t	CLOCK_DeinitFirc (void)
	De-initializes the SCG fast IRC.
static void	CLOCK_SetFircAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider.
uint32_t	CLOCK_GetFircFreq (void)
	Gets the SCG FIRC clock frequency.
uint32_t	CLOCK_GetFircAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the FIRC.
static bool	CLOCK_IsFircErr (void)
	Checks whether the FIRC clock error occurs.
static void	CLOCK_ClearFircErr (void)
	Clears the FIRC clock error.
static bool	CLOCK_IsFircValid (void)
	Checks whether the FIRC clock is valid.

SCG System PLL Clock.
uint32_t	CLOCK_GetSysPllMultDiv (uint32_t refFreq, uint32_t desireFreq, uint8_t *mult, uint8_t *prediv)
	Calculates the MULT and PREDIV for the PLL.
status_t	CLOCK_InitSysPll (const scg_spll_config_t *config)
	Initializes the SCG system PLL.
status_t	CLOCK_DeinitSysPll (void)
	De-initializes the SCG system PLL.
static void	CLOCK_SetSysPllAsyncClkDiv (scg_async_clk_t asyncClk, scg_async_clk_div_t divider)
	Set the asynchronous clock divider.
uint32_t	CLOCK_GetSysPllFreq (void)
	Gets the SCG system PLL clock frequency.
uint32_t	CLOCK_GetSysPllAsyncFreq (scg_async_clk_t type)
	Gets the SCG asynchronous clock frequency from the system PLL.
static bool	CLOCK_IsSysPllErr (void)
	Checks whether the system PLL clock error occurs.
static void	CLOCK_ClearSysPllErr (void)
	Clears the system PLL clock error.
static void	CLOCK_SetSysPllMonitorMode (scg_spll_monitor_mode_t mode)
	Sets the system PLL monitor mode.
static bool	CLOCK_IsSysPllValid (void)
	Checks whether the system PLL clock is valid.

OSC32 operations
void	OSC32_Init (OSC32_Type *base, osc32_mode_t mode)
	Initializes OSC32.
void	OSC32_Deinit (OSC32_Type *base)
	Deinitializes OSC32.

External clock frequency
static void	CLOCK_SetXtal0Freq (uint32_t freq)
	Sets the XTAL0 frequency based on board settings.
static void	CLOCK_SetXtal32Freq (uint32_t freq)
	Sets the XTAL32 frequency based on board settings.

Detailed Description

Typedef Documentation

clock_clkout_src_t

typedef enum _clock_clkout_src clock_clkout_src_t

SCG clock out configuration (CLKOUTSEL).

clock_ip_name_t

typedef enum _clock_ip_name clock_ip_name_t

Peripheral clock name difinition used for clock gate, clock source and clock divider setting. It is defined as the corresponding register address.

clock_ip_src_t

typedef enum _clock_ip_src clock_ip_src_t

Clock source for peripherals that support various clock selections.

clock_name_t

typedef enum _clock_name clock_name_t

Clock name used to get clock frequency.

osc32_mode_t

typedef enum _osc32_mode osc32_mode_t

OSC32 work mode.

scg_async_clk_div_t

typedef enum scg_async_clk_div scg_async_clk_div_t

SCG asynchronous clock divider value.

scg_async_clk_t

typedef enum _scg_async_clk scg_async_clk_t

SCG asynchronous clock type.

scg_firc_config_t

typedef struct _scg_firc_config_t scg_firc_config_t

SCG fast IRC clock configuration.

scg_firc_range_t

typedef enum _scg_firc_range scg_firc_range_t

SCG fast IRC clock frequency range.

scg_firc_trim_config_t

typedef struct _scg_firc_trim_config scg_firc_trim_config_t

SCG fast IRC clock trim configuration.

scg_firc_trim_div_t

typedef enum _scg_firc_trim_div scg_firc_trim_div_t

SCG fast IRC trim predivided value for system OSC.

scg_firc_trim_mode_t

typedef enum _scg_firc_trim_mode scg_firc_trim_mode_t

SCG fast IRC trim mode.

scg_firc_trim_src_t

typedef enum _scg_firc_trim_src scg_firc_trim_src_t

SCG fast IRC trim source.

scg_sirc_config_t

typedef struct _scg_sirc_config scg_sirc_config_t

SCG slow IRC clock configuration.

scg_sirc_range_t

typedef enum _scg_sirc_range scg_sirc_range_t

SCG slow IRC clock frequency range.

scg_sosc_config_t

typedef struct _scg_sosc_config scg_sosc_config_t

SCG system OSC configuration.

scg_sosc_mode_t

typedef enum _scg_sosc_mode scg_sosc_mode_t

OSC work mode.

scg_sosc_monitor_mode_t

typedef enum _scg_sosc_monitor_mode scg_sosc_monitor_mode_t

SCG system OSC monitor mode.

scg_spll_config_t

typedef struct _scg_spll_config scg_spll_config_t

SCG system PLL configuration.

scg_spll_monitor_mode_t

typedef enum _scg_spll_monitor_mode scg_spll_monitor_mode_t

SCG system PLL monitor mode.

scg_spll_src_t

typedef enum _scg_spll_src scg_spll_src_t

SCG system PLL clock source.

scg_sys_clk_config_t

typedef struct _scg_sys_clk_config scg_sys_clk_config_t

SCG system clock configuration.

scg_sys_clk_div_t

typedef enum _scg_sys_clk_div scg_sys_clk_div_t

SCG system clock divider value.

scg_sys_clk_src_t

typedef enum _scg_sys_clk_src scg_sys_clk_src_t

SCG system clock source.

scg_sys_clk_t

typedef enum _scg_sys_clk scg_sys_clk_t

SCG system clock type.

Enumeration Type Documentation

_clock_clkout_src

enum _clock_clkout_src

SCG clock out configuration (CLKOUTSEL).

Enumerator
kClockClkoutSelScgSlow	SCG slow clock.
kClockClkoutSelSysOsc	System OSC.
kClockClkoutSelSirc	Slow IRC.
kClockClkoutSelFirc	Fast IRC.
kClockClkoutSelSysPll	System PLL.

Definition at line 395 of file fsl_clock.h.

{
    kClockClkoutSelScgSlow = 0U, /*!< SCG slow clock. */
    kClockClkoutSelSysOsc = 1U,  /*!< System OSC.     */
    kClockClkoutSelSirc = 2U,    /*!< Slow IRC.       */
    kClockClkoutSelFirc = 3U,    /*!< Fast IRC.       */
    kClockClkoutSelSysPll = 6U   /*!< System PLL.     */
} clock_clkout_src_t;

_clock_ip_name

enum _clock_ip_name

Peripheral clock name difinition used for clock gate, clock source and clock divider setting. It is defined as the corresponding register address.

Enumerator
kCLOCK_IpInvalid
kCLOCK_Dma0
kCLOCK_Sysmpu0
kCLOCK_Flash0
kCLOCK_Dmamux0
kCLOCK_Flexcan0
kCLOCK_Flexcan1
kCLOCK_Ftm3
kCLOCK_Adc1
kCLOCK_Lpspi0
kCLOCK_Lpspi1
kCLOCK_Pdb1
kCLOCK_Crc0
kCLOCK_Pdb2
kCLOCK_Pdb0
kCLOCK_Lpit0
kCLOCK_Ftm0
kCLOCK_Ftm1
kCLOCK_Ftm2
kCLOCK_Adc0
kCLOCK_Adc2
kCLOCK_Rtc0
kCLOCK_Dac0
kCLOCK_Lptmr0
kCLOCK_PortA
kCLOCK_PortB
kCLOCK_PortC
kCLOCK_PortD
kCLOCK_PortE
kCLOCK_Pwt0
kCLOCK_Flexio0
kCLOCK_RtcOsc0
kCLOCK_Ewm0
kCLOCK_Lpi2c0
kCLOCK_Lpi2c1
kCLOCK_Lpuart0
kCLOCK_Lpuart1
kCLOCK_Lpuart2
kCLOCK_Cmp0
kCLOCK_Cmp1
kCLOCK_Cmp2

Definition at line 266 of file fsl_clock.h.

{
    kCLOCK_IpInvalid = 0U,
 
    /* PCC 0 */
    kCLOCK_Dma0 = 0x40065020U,
    kCLOCK_Sysmpu0 = 0x40065034U,
    kCLOCK_Flash0 = 0x40065080U,
    kCLOCK_Dmamux0 = 0x40065084U,
    kCLOCK_Flexcan0 = 0x40065090U,
    kCLOCK_Flexcan1 = 0x40065094U,
    kCLOCK_Ftm3 = 0x40065098U,
    kCLOCK_Adc1 = 0x4006509CU,
    kCLOCK_Lpspi0 = 0x400650B0U,
    kCLOCK_Lpspi1 = 0x400650B4U,
    kCLOCK_Pdb1 = 0x400650C4U,
    kCLOCK_Crc0 = 0x400650C8U,
    kCLOCK_Pdb2 = 0x400650CCU,
    kCLOCK_Pdb0 = 0x400650D8U,
    kCLOCK_Lpit0 = 0x400650DCU,
    kCLOCK_Ftm0 = 0x400650E0U,
    kCLOCK_Ftm1 = 0x400650E4U,
    kCLOCK_Ftm2 = 0x400650E8U,
    kCLOCK_Adc0 = 0x400650ECU,
    kCLOCK_Adc2 = 0x400650F0U,
    kCLOCK_Rtc0 = 0x400650F4U,
    kCLOCK_Dac0 = 0x400650FCU,
    kCLOCK_Lptmr0 = 0x40065100U,
    kCLOCK_PortA = 0x40065124U,
    kCLOCK_PortB = 0x40065128U,
    kCLOCK_PortC = 0x4006512CU,
    kCLOCK_PortD = 0x40065130U,
    kCLOCK_PortE = 0x40065134U,
    kCLOCK_Pwt0 = 0x40065158U,
    kCLOCK_Flexio0 = 0x40065168U,
    kCLOCK_RtcOsc0 = 0x40065180U,
    kCLOCK_Ewm0 = 0x40065184U,
    kCLOCK_Lpi2c0 = 0x40065198U,
    kCLOCK_Lpi2c1 = 0x4006519CU,
    kCLOCK_Lpuart0 = 0x400651A8U,
    kCLOCK_Lpuart1 = 0x400651ACU,
    kCLOCK_Lpuart2 = 0x400651B0U,
    kCLOCK_Cmp0 = 0x400651CCU,
    kCLOCK_Cmp1 = 0x400651D0U,
    kCLOCK_Cmp2 = 0x400651D4U,
} clock_ip_name_t;

_clock_ip_src

enum _clock_ip_src

Clock source for peripherals that support various clock selections.

Enumerator
kCLOCK_IpSrcNoneOrExt	Clock is off or external clock is used.
kCLOCK_IpSrcSysOscAsync	System Oscillator async clock.
kCLOCK_IpSrcSircAsync	Slow IRC async clock.
kCLOCK_IpSrcFircAsync	Fast IRC async clock.
kCLOCK_IpSrcSysPllAsync	System PLL async clock.

Definition at line 253 of file fsl_clock.h.

{
    kCLOCK_IpSrcNoneOrExt = 0U,   /*!< Clock is off or external clock is used. */
    kCLOCK_IpSrcSysOscAsync = 1U, /*!< System Oscillator async clock.          */
    kCLOCK_IpSrcSircAsync = 2U,   /*!< Slow IRC async clock.                   */
    kCLOCK_IpSrcFircAsync = 3U,   /*!< Fast IRC async clock.                   */
    kCLOCK_IpSrcSysPllAsync = 6U  /*!< System PLL async clock.                 */
} clock_ip_src_t;

_clock_name

enum _clock_name

Clock name used to get clock frequency.

Enumerator
kCLOCK_CoreSysClk	Core/system clock
kCLOCK_BusClk	Bus clock
kCLOCK_FlexBusClk	FlexBus clock
kCLOCK_FlashClk	Flash clock
kCLOCK_ScgSysOscClk	SCG system OSC clock. (SYSOSC)
kCLOCK_ScgSircClk	SCG SIRC clock.
kCLOCK_ScgFircClk	SCG FIRC clock.
kCLOCK_ScgSysPllClk	SCG system PLL clock. (SYSPLL)
kCLOCK_ScgSysOscAsyncDiv1Clk	SOSCDIV1_CLK.
kCLOCK_ScgSysOscAsyncDiv2Clk	SOSCDIV2_CLK.
kCLOCK_ScgSircAsyncDiv1Clk	SIRCDIV1_CLK.
kCLOCK_ScgSircAsyncDiv2Clk	SIRCDIV2_CLK.
kCLOCK_ScgFircAsyncDiv1Clk	FIRCDIV1_CLK.
kCLOCK_ScgFircAsyncDiv2Clk	FIRCDIV2_CLK.
kCLOCK_ScgSysPllAsyncDiv1Clk	SPLLDIV1_CLK.
kCLOCK_ScgSysPllAsyncDiv2Clk	SPLLDIV2_CLK.
kCLOCK_LpoClk	LPO clock
kCLOCK_Osc32kClk	External OSC 32K clock (OSC32KCLK)
kCLOCK_ErClk	ERCLK. The external reference clock from SCG.

Definition at line 213 of file fsl_clock.h.

{
    /* ----------------------------- System layer clock -------------------------------*/
    kCLOCK_CoreSysClk, /*!< Core/system clock                                   */
    kCLOCK_BusClk,     /*!< Bus clock                                           */
    kCLOCK_FlexBusClk, /*!< FlexBus clock                                       */
    kCLOCK_FlashClk,   /*!< Flash clock                                         */
 
    /* ------------------------------------ SCG clock ---------------------------------*/
    kCLOCK_ScgSysOscClk, /*!< SCG system OSC clock. (SYSOSC)                      */
    kCLOCK_ScgSircClk,   /*!< SCG SIRC clock.                                     */
    kCLOCK_ScgFircClk,   /*!< SCG FIRC clock.                                     */
    kCLOCK_ScgSysPllClk, /*!< SCG system PLL clock. (SYSPLL)                      */
 
    kCLOCK_ScgSysOscAsyncDiv1Clk, /*!< SOSCDIV1_CLK.                                   */
    kCLOCK_ScgSysOscAsyncDiv2Clk, /*!< SOSCDIV2_CLK.                                   */
 
    kCLOCK_ScgSircAsyncDiv1Clk, /*!< SIRCDIV1_CLK.                                   */
    kCLOCK_ScgSircAsyncDiv2Clk, /*!< SIRCDIV2_CLK.                                   */
 
    kCLOCK_ScgFircAsyncDiv1Clk, /*!< FIRCDIV1_CLK.                                   */
    kCLOCK_ScgFircAsyncDiv2Clk, /*!< FIRCDIV2_CLK.                                   */
 
    kCLOCK_ScgSysPllAsyncDiv1Clk, /*!< SPLLDIV1_CLK.                                   */
    kCLOCK_ScgSysPllAsyncDiv2Clk, /*!< SPLLDIV2_CLK.                                   */
 
    /* --------------------------------- Other clock ----------------------------------*/
    kCLOCK_LpoClk,    /*!< LPO clock                                           */
    kCLOCK_Osc32kClk, /*!< External OSC 32K clock (OSC32KCLK)                  */
    kCLOCK_ErClk,     /*!< ERCLK. The external reference clock from SCG.       */
} clock_name_t;

_osc32_mode

enum _osc32_mode

OSC32 work mode.

Enumerator
kOSC32_Bypass	Bypass mode, use external input clock directly.
kOSC32_Crystal	Crystal mode, does not work in stop mode.
kOSC32_CrystalEnableInStop	Crystal mode, still work in stop mode.

Definition at line 316 of file fsl_clock.h.

{
    kOSC32_Bypass = OSC32_CR_ROSCEN_MASK, /*!< Bypass mode, use external input clock directly. */
    kOSC32_Crystal = OSC32_CR_ROSCEN_MASK | OSC32_CR_ROSCEREFS_MASK, /*!< Crystal mode, does not work in stop mode. */
    kOSC32_CrystalEnableInStop = OSC32_CR_ROSCEN_MASK | OSC32_CR_ROSCSTPEN_MASK |
                                 OSC32_CR_ROSCEREFS_MASK, /*!< Crystal mode, still work in stop mode. */
} osc32_mode_t;

_scg_async_clk

enum _scg_async_clk

SCG asynchronous clock type.

Enumerator
kSCG_AsyncDiv1Clk	The async clock by DIV1, e.g. SOSCDIV1_CLK, SIRCDIV1_CLK.
kSCG_AsyncDiv2Clk	The async clock by DIV2, e.g. SOSCDIV2_CLK, SIRCDIV2_CLK.

Definition at line 407 of file fsl_clock.h.

{
    kSCG_AsyncDiv1Clk, /*!< The async clock by DIV1, e.g. SOSCDIV1_CLK, SIRCDIV1_CLK. */
    kSCG_AsyncDiv2Clk, /*!< The async clock by DIV2, e.g. SOSCDIV2_CLK, SIRCDIV2_CLK. */
} scg_async_clk_t;

_scg_firc_enable_mode

enum _scg_firc_enable_mode

FIRC enable mode.

Enumerator
kSCG_FircEnable	Enable FIRC clock.
kSCG_FircEnableInStop	Enable FIRC in stop mode.
kSCG_FircEnableInLowPower	Enable FIRC in low power mode.
kSCG_FircDisableRegulator	Disable regulator.

Definition at line 562 of file fsl_clock.h.

{
    kSCG_FircEnable = SCG_FIRCCSR_FIRCEN_MASK,              /*!< Enable FIRC clock.             */
    kSCG_FircEnableInStop = SCG_FIRCCSR_FIRCSTEN_MASK,      /*!< Enable FIRC in stop mode.      */
    kSCG_FircEnableInLowPower = SCG_FIRCCSR_FIRCLPEN_MASK,  /*!< Enable FIRC in low power mode. */
    kSCG_FircDisableRegulator = SCG_FIRCCSR_FIRCREGOFF_MASK /*!< Disable regulator.             */
};

_scg_firc_range

enum _scg_firc_range

SCG fast IRC clock frequency range.

Enumerator
kSCG_FircRange48M	Fast IRC is trimmed to 48 MHz.
kSCG_FircRange52M	Fast IRC is trimmed to 52 MHz.
kSCG_FircRange56M	Fast IRC is trimmed to 56 MHz.
kSCG_FircRange60M	Fast IRC is trimmed to 60 MHz.

Definition at line 553 of file fsl_clock.h.

{
    kSCG_FircRange48M, /*!< Fast IRC is trimmed to 48 MHz.  */
    kSCG_FircRange52M, /*!< Fast IRC is trimmed to 52 MHz.  */
    kSCG_FircRange56M, /*!< Fast IRC is trimmed to 56 MHz.  */
    kSCG_FircRange60M  /*!< Fast IRC is trimmed to 60 MHz.  */
} scg_firc_range_t;

_scg_firc_trim_div

enum _scg_firc_trim_div

SCG fast IRC trim predivided value for system OSC.

Enumerator
kSCG_FircTrimDivBy1	Divided by 1.
kSCG_FircTrimDivBy128	Divided by 128.
kSCG_FircTrimDivBy256	Divided by 256.
kSCG_FircTrimDivBy512	Divided by 512.
kSCG_FircTrimDivBy1024	Divided by 1024.
kSCG_FircTrimDivBy2048	Divided by 2048.

Definition at line 519 of file fsl_clock.h.

{
    kSCG_FircTrimDivBy1,    /*!< Divided by 1.    */
    kSCG_FircTrimDivBy128,  /*!< Divided by 128.  */
    kSCG_FircTrimDivBy256,  /*!< Divided by 256.  */
    kSCG_FircTrimDivBy512,  /*!< Divided by 512.  */
    kSCG_FircTrimDivBy1024, /*!< Divided by 1024. */
    kSCG_FircTrimDivBy2048  /*!< Divided by 2048. */
} scg_firc_trim_div_t;

_scg_firc_trim_mode

enum _scg_firc_trim_mode

SCG fast IRC trim mode.

Enumerator
kSCG_FircTrimNonUpdate	FIRC trim enable but not enable trim value update. In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure scg_firc_trim_config_t.
kSCG_FircTrimUpdate	FIRC trim enable and trim value update enable. In this mode, the trim value is auto update.

Definition at line 503 of file fsl_clock.h.

{
    kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK,
    /*!< FIRC trim enable but not enable trim value update. In this mode, the
     trim value is fixed to the initialized value which is defined by
     trimCoar and trimFine in configure structure \ref scg_firc_trim_config_t.*/
 
    kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK
    /*!< FIRC trim enable and trim value update enable. In this mode, the trim
     value is auto update. */
 
} scg_firc_trim_mode_t;

_scg_firc_trim_src

enum _scg_firc_trim_src

SCG fast IRC trim source.

Enumerator
kSCG_FircTrimSrcSysOsc	System OSC.

Definition at line 532 of file fsl_clock.h.

{
    kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC.                 */
} scg_firc_trim_src_t;

_scg_sirc_enable_mode

enum _scg_sirc_enable_mode

SIRC enable mode.

Enumerator
kSCG_SircEnable	Enable SIRC clock.
kSCG_SircEnableInStop	Enable SIRC in stop mode.
kSCG_SircEnableInLowPower	Enable SIRC in low power mode.

Definition at line 481 of file fsl_clock.h.

{
    kSCG_SircEnable = SCG_SIRCCSR_SIRCEN_MASK,            /*!< Enable SIRC clock.             */
    kSCG_SircEnableInStop = SCG_SIRCCSR_SIRCSTEN_MASK,    /*!< Enable SIRC in stop mode.      */
    kSCG_SircEnableInLowPower = SCG_SIRCCSR_SIRCLPEN_MASK /*!< Enable SIRC in low power mode. */
};

_scg_sirc_range

enum _scg_sirc_range

SCG slow IRC clock frequency range.

Enumerator
kSCG_SircRangeLow	Slow IRC low range clock (2 MHz, 4 MHz for i.MX 7 ULP).
kSCG_SircRangeHigh	Slow IRC high range clock (8 MHz, 16 MHz for i.MX 7 ULP).

Definition at line 474 of file fsl_clock.h.

{
    kSCG_SircRangeLow, /*!< Slow IRC low range clock (2 MHz, 4 MHz for i.MX 7 ULP).  */
    kSCG_SircRangeHigh /*!< Slow IRC high range clock (8 MHz, 16 MHz for i.MX 7 ULP). */
} scg_sirc_range_t;

_scg_sosc_enable_mode

enum _scg_sosc_enable_mode

OSC enable mode.

Enumerator
kSCG_SysOscEnable	Enable OSC clock.
kSCG_SysOscEnableInStop	Enable OSC in stop mode.
kSCG_SysOscEnableInLowPower	Enable OSC in low power mode.
kSCG_SysOscEnableErClk	Enable OSCERCLK.

Definition at line 448 of file fsl_clock.h.

{
    kSCG_SysOscEnable = SCG_SOSCCSR_SOSCEN_MASK,             /*!< Enable OSC clock. */
    kSCG_SysOscEnableInStop = SCG_SOSCCSR_SOSCSTEN_MASK,     /*!< Enable OSC in stop mode. */
    kSCG_SysOscEnableInLowPower = SCG_SOSCCSR_SOSCLPEN_MASK, /*!< Enable OSC in low power mode. */
    kSCG_SysOscEnableErClk = SCG_SOSCCSR_SOSCERCLKEN_MASK    /*!< Enable OSCERCLK. */
};

_scg_sosc_mode

enum _scg_sosc_mode

OSC work mode.

Enumerator
kSCG_SysOscModeExt	Use external clock.
kSCG_SysOscModeOscLowPower	Oscillator low power.
kSCG_SysOscModeOscHighGain	Oscillator high gain.

Definition at line 440 of file fsl_clock.h.

{
    kSCG_SysOscModeExt = 0U,                                                   /*!< Use external clock.   */
    kSCG_SysOscModeOscLowPower = SCG_SOSCCFG_EREFS_MASK,                       /*!< Oscillator low power. */
    kSCG_SysOscModeOscHighGain = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_HGO_MASK /*!< Oscillator high gain. */
} scg_sosc_mode_t;

_scg_sosc_monitor_mode

enum _scg_sosc_monitor_mode

SCG system OSC monitor mode.

Enumerator
kSCG_SysOscMonitorDisable	Monitor disabled.
kSCG_SysOscMonitorInt	Interrupt when the system OSC error is detected.
kSCG_SysOscMonitorReset	Reset when the system OSC error is detected.

Definition at line 431 of file fsl_clock.h.

{
    kSCG_SysOscMonitorDisable = 0U,                  /*!< Monitor disabled.                          */
    kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the system OSC error is detected. */
    kSCG_SysOscMonitorReset =
        SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the system OSC error is detected.     */
} scg_sosc_monitor_mode_t;

_scg_spll_enable_mode

enum _scg_spll_enable_mode

SPLL enable mode.

Enumerator
kSCG_SysPllEnable	Enable SPLL clock.
kSCG_SysPllEnableInStop	Enable SPLL in stop mode.

Definition at line 606 of file fsl_clock.h.

{
    kSCG_SysPllEnable = SCG_SPLLCSR_SPLLEN_MASK,        /*!< Enable SPLL clock.             */
    kSCG_SysPllEnableInStop = SCG_SPLLCSR_SPLLSTEN_MASK /*!< Enable SPLL in stop mode.      */
};

_scg_spll_monitor_mode

enum _scg_spll_monitor_mode

SCG system PLL monitor mode.

Enumerator
kSCG_SysPllMonitorDisable	Monitor disabled.
kSCG_SysPllMonitorInt	Interrupt when the system PLL error is detected.
kSCG_SysPllMonitorReset	Reset when the system PLL error is detected.

Definition at line 597 of file fsl_clock.h.

{
    kSCG_SysPllMonitorDisable = 0U,                  /*!< Monitor disabled.                          */
    kSCG_SysPllMonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the system PLL error is detected. */
    kSCG_SysPllMonitorReset =
        SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the system PLL error is detected.     */
} scg_spll_monitor_mode_t;

_scg_spll_src

enum _scg_spll_src

SCG system PLL clock source.

Enumerator
kSCG_SysPllSrcSysOsc	System PLL clock source is system OSC.
kSCG_SysPllSrcFirc	System PLL clock source is fast IRC.

Definition at line 588 of file fsl_clock.h.

{
    kSCG_SysPllSrcSysOsc, /*!< System PLL clock source is system OSC. */
    kSCG_SysPllSrcFirc    /*!< System PLL clock source is fast IRC.   */
} scg_spll_src_t;

_scg_status

enum _scg_status

SCG status return codes.

Enumerator
kStatus_SCG_Busy	Clock is busy.
kStatus_SCG_InvalidSrc	Invalid source.

Definition at line 327 of file fsl_clock.h.

{
    kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1),      /*!< Clock is busy.  */
    kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */
};

_scg_sys_clk

enum _scg_sys_clk

SCG system clock type.

Enumerator
kSCG_SysClkSlow	System slow clock.
kSCG_SysClkBus	Bus clock.
kSCG_SysClkCore	Core clock.

Definition at line 336 of file fsl_clock.h.

{
    kSCG_SysClkSlow, /*!< System slow clock. */
    kSCG_SysClkBus,  /*!< Bus clock.         */
    kSCG_SysClkCore, /*!< Core clock.        */
} scg_sys_clk_t;

_scg_sys_clk_div

enum _scg_sys_clk_div

SCG system clock divider value.

Enumerator
kSCG_SysClkDivBy1	Divided by 1.
kSCG_SysClkDivBy2	Divided by 2.
kSCG_SysClkDivBy3	Divided by 3.
kSCG_SysClkDivBy4	Divided by 4.
kSCG_SysClkDivBy5	Divided by 5.
kSCG_SysClkDivBy6	Divided by 6.
kSCG_SysClkDivBy7	Divided by 7.
kSCG_SysClkDivBy8	Divided by 8.
kSCG_SysClkDivBy9	Divided by 9.
kSCG_SysClkDivBy10	Divided by 10.
kSCG_SysClkDivBy11	Divided by 11.
kSCG_SysClkDivBy12	Divided by 12.
kSCG_SysClkDivBy13	Divided by 13.
kSCG_SysClkDivBy14	Divided by 14.
kSCG_SysClkDivBy15	Divided by 15.
kSCG_SysClkDivBy16	Divided by 16.

Definition at line 357 of file fsl_clock.h.

{
    kSCG_SysClkDivBy1 = 0U,   /*!< Divided by 1.  */
    kSCG_SysClkDivBy2 = 1U,   /*!< Divided by 2.  */
    kSCG_SysClkDivBy3 = 2U,   /*!< Divided by 3.  */
    kSCG_SysClkDivBy4 = 3U,   /*!< Divided by 4.  */
    kSCG_SysClkDivBy5 = 4U,   /*!< Divided by 5.  */
    kSCG_SysClkDivBy6 = 5U,   /*!< Divided by 6.  */
    kSCG_SysClkDivBy7 = 6U,   /*!< Divided by 7.  */
    kSCG_SysClkDivBy8 = 7U,   /*!< Divided by 8.  */
    kSCG_SysClkDivBy9 = 8U,   /*!< Divided by 9.  */
    kSCG_SysClkDivBy10 = 9U,  /*!< Divided by 10. */
    kSCG_SysClkDivBy11 = 10U, /*!< Divided by 11. */
    kSCG_SysClkDivBy12 = 11U, /*!< Divided by 12. */
    kSCG_SysClkDivBy13 = 12U, /*!< Divided by 13. */
    kSCG_SysClkDivBy14 = 13U, /*!< Divided by 14. */
    kSCG_SysClkDivBy15 = 14U, /*!< Divided by 15. */
    kSCG_SysClkDivBy16 = 15U  /*!< Divided by 16. */
} scg_sys_clk_div_t;

_scg_sys_clk_src

enum _scg_sys_clk_src

SCG system clock source.

Enumerator
kSCG_SysClkSrcSysOsc	System OSC.
kSCG_SysClkSrcSirc	Slow IRC.
kSCG_SysClkSrcFirc	Fast IRC.
kSCG_SysClkSrcSysPll	System PLL.

Definition at line 346 of file fsl_clock.h.

{
    kSCG_SysClkSrcSysOsc = 1U, /*!< System OSC. */
    kSCG_SysClkSrcSirc = 2U,   /*!< Slow IRC.   */
    kSCG_SysClkSrcFirc = 3U,   /*!< Fast IRC.   */
    kSCG_SysClkSrcSysPll = 6U  /*!< System PLL. */
} scg_sys_clk_src_t;

scg_async_clk_div

enum scg_async_clk_div

SCG asynchronous clock divider value.

Enumerator
kSCG_AsyncClkDisable	Clock output is disabled.
kSCG_AsyncClkDivBy1	Divided by 1.
kSCG_AsyncClkDivBy2	Divided by 2.
kSCG_AsyncClkDivBy4	Divided by 4.
kSCG_AsyncClkDivBy8	Divided by 8.
kSCG_AsyncClkDivBy16	Divided by 16.
kSCG_AsyncClkDivBy32	Divided by 32.
kSCG_AsyncClkDivBy64	Divided by 64.

Definition at line 416 of file fsl_clock.h.

{
    kSCG_AsyncClkDisable = 0U, /*!< Clock output is disabled.  */
    kSCG_AsyncClkDivBy1 = 1U,  /*!< Divided by 1.              */
    kSCG_AsyncClkDivBy2 = 2U,  /*!< Divided by 2.              */
    kSCG_AsyncClkDivBy4 = 3U,  /*!< Divided by 4.              */
    kSCG_AsyncClkDivBy8 = 4U,  /*!< Divided by 8.              */
    kSCG_AsyncClkDivBy16 = 5U, /*!< Divided by 16.             */
    kSCG_AsyncClkDivBy32 = 6U, /*!< Divided by 32.             */
    kSCG_AsyncClkDivBy64 = 7U  /*!< Divided by 64.             */
} scg_async_clk_div_t;

Function Documentation

CLOCK_ClearFircErr()

static void CLOCK_ClearFircErr ( void  )

inlinestatic

Clears the FIRC clock error.

Definition at line 1140 of file fsl_clock.h.

{
    SCG->FIRCCSR |= SCG_FIRCCSR_FIRCERR_MASK;
}

CLOCK_ClearSysOscErr()

static void CLOCK_ClearSysOscErr ( void  )

inlinestatic

Clears the system OSC clock error.

Definition at line 932 of file fsl_clock.h.

{
    SCG->SOSCCSR |= SCG_SOSCCSR_SOSCERR_MASK;
}

CLOCK_ClearSysPllErr()

static void CLOCK_ClearSysPllErr ( void  )

inlinestatic

Clears the system PLL clock error.

Definition at line 1282 of file fsl_clock.h.

{
    SCG->SPLLCSR |= SCG_SPLLCSR_SPLLERR_MASK;
}

CLOCK_DeinitFirc()

status_t CLOCK_DeinitFirc

(

void

)

De-initializes the SCG fast IRC.

This function disables the SCG fast IRC.

Return values

kStatus_Success	FIRC is deinitialized.
kStatus_SCG_Busy	FIRC is used by the system clock.
kStatus_ReadOnly	FIRC control register is locked.

Note

This function can't detect whether the FIRC is used by an IP.

brief De-initializes the SCG fast IRC.

This function disables the SCG fast IRC.

retval kStatus_Success FIRC is deinitialized. retval kStatus_SCG_Busy FIRC is used by the system clock. retval kStatus_ReadOnly FIRC control register is locked.

note This function can't detect whether the FIRC is used by an IP.

Definition at line 755 of file fsl_clock.c.

{
    uint32_t reg = SCG->FIRCCSR;
 
    /* If clock is used by system, return error. */
    if (reg & SCG_FIRCCSR_FIRCSEL_MASK)
    {
        return kStatus_SCG_Busy;
    }
 
    /* If configure register is locked, return error. */
    if (reg & SCG_FIRCCSR_LK_MASK)
    {
        return kStatus_ReadOnly;
    }
 
    SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK;
 
    return kStatus_Success;
}

Referenced by CLOCK_InitFirc().

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CLOCK_DeinitSirc()

status_t CLOCK_DeinitSirc

(

void

)

De-initializes the SCG slow IRC.

This function disables the SCG slow IRC.

Return values

kStatus_Success	SIRC is deinitialized.
kStatus_SCG_Busy	SIRC is used by system clock.
kStatus_ReadOnly	SIRC control register is locked.

Note

This function can't detect whether the SIRC is used by an IP.

brief De-initializes the SCG slow IRC.

This function disables the SCG slow IRC.

retval kStatus_Success SIRC is deinitialized. retval kStatus_SCG_Busy SIRC is used by system clock. retval kStatus_ReadOnly SIRC control register is locked.

note This function can't detect whether the SIRC is used by an IP.

Definition at line 601 of file fsl_clock.c.

{
    uint32_t reg = SCG->SIRCCSR;
 
    /* If clock is used by system, return error. */
    if (reg & SCG_SIRCCSR_SIRCSEL_MASK)
    {
        return kStatus_SCG_Busy;
    }
 
    /* If configure register is locked, return error. */
    if (reg & SCG_SIRCCSR_LK_MASK)
    {
        return kStatus_ReadOnly;
    }
 
    SCG->SIRCCSR = 0U;
 
    return kStatus_Success;
}

Referenced by CLOCK_InitSirc().

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CLOCK_DeinitSysOsc()

status_t CLOCK_DeinitSysOsc

(

void

)

De-initializes the SCG system OSC.

This function disables the SCG system OSC clock.

Return values

kStatus_Success	System OSC is deinitialized.
kStatus_SCG_Busy	System OSC is used by the system clock.
kStatus_ReadOnly	System OSC control register is locked.

Note

This function can't detect whether the system OSC is used by an IP.

brief De-initializes the SCG system OSC.

This function disables the SCG system OSC clock.

retval kStatus_Success System OSC is deinitialized. retval kStatus_SCG_Busy System OSC is used by the system clock. retval kStatus_ReadOnly System OSC control register is locked.

note This function can't detect whether the system OSC is used by an IP.

Definition at line 468 of file fsl_clock.c.

{
    uint32_t reg = SCG->SOSCCSR;
 
    /* If clock is used by system, return error. */
    if (reg & SCG_SOSCCSR_SOSCSEL_MASK)
    {
        return kStatus_SCG_Busy;
    }
 
    /* If configure register is locked, return error. */
    if (reg & SCG_SOSCCSR_LK_MASK)
    {
        return kStatus_ReadOnly;
    }
 
    SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
 
    return kStatus_Success;
}

Referenced by CLOCK_InitSysOsc().

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CLOCK_DeinitSysPll()

status_t CLOCK_DeinitSysPll

(

void

)

De-initializes the SCG system PLL.

This function disables the SCG system PLL.

Return values

kStatus_Success	system PLL is deinitialized.
kStatus_SCG_Busy	system PLL is used by the system clock.
kStatus_ReadOnly	System PLL control register is locked.

Note

This function can't detect whether the system PLL is used by an IP.

brief De-initializes the SCG system PLL.

This function disables the SCG system PLL.

retval kStatus_Success system PLL is deinitialized. retval kStatus_SCG_Busy system PLL is used by the system clock. retval kStatus_ReadOnly System PLL control register is locked.

note This function can't detect whether the system PLL is used by an IP.

Definition at line 1031 of file fsl_clock.c.

{
    uint32_t reg = SCG->SPLLCSR;
 
    /* If clock is used by system, return error. */
    if (reg & SCG_SPLLCSR_SPLLSEL_MASK)
    {
        return kStatus_SCG_Busy;
    }
 
    /* If configure register is locked, return error. */
    if (reg & SCG_SPLLCSR_LK_MASK)
    {
        return kStatus_ReadOnly;
    }
 
    /* Deinit and clear the error. */
    SCG->SPLLCSR = SCG_SPLLCSR_SPLLERR_MASK;
 
    return kStatus_Success;
}

Referenced by CLOCK_InitSysPll().

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CLOCK_DisableClock()

static void CLOCK_DisableClock ( clock_ip_name_t  name )

inlinestatic

Disable the clock for specific IP.

Parameters

name	Which clock to disable, see clock_ip_name_t.

Definition at line 653 of file fsl_clock.h.

{
    assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK);
 
    (*(volatile uint32_t *)name) &= ~PCC_CLKCFG_CGC_MASK;
}

Referenced by ACMP_Deinit(), ADC12_Deinit(), DMAMUX_Deinit(), EDMA_Deinit(), LPSPI_Deinit(), LPUART_Deinit(), and OSC32_Deinit().

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CLOCK_EnableClock()

static void CLOCK_EnableClock ( clock_ip_name_t  name )

inlinestatic

Enable the clock for specific IP.

Parameters

name	Which clock to enable, see clock_ip_name_t.

Definition at line 641 of file fsl_clock.h.

{
    assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK);
 
    (*(volatile uint32_t *)name) |= PCC_CLKCFG_CGC_MASK;
}

Referenced by ACMP_Init(), ADC12_Init(), DMAMUX_Init(), EDMA_Init(), LPSPI_MasterInit(), LPSPI_SlaveInit(), LPUART_Init(), OSC32_Init(), and pwm_lld_start().

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CLOCK_GetBusClkFreq()

uint32_t CLOCK_GetBusClkFreq

(

void

)

Get the bus clock frequency.

Returns

Clock frequency in Hz.

brief Get the bus clock frequency.

return Clock frequency in Hz.

Definition at line 144 of file fsl_clock.c.

{
    return CLOCK_GetSysClkFreq(kSCG_SysClkBus);
}

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CLOCK_GetCoreSysClkFreq()

uint32_t CLOCK_GetCoreSysClkFreq

(

void

)

Get the core clock or system clock frequency.

Returns

Clock frequency in Hz.

brief Get the core clock or system clock frequency.

return Clock frequency in Hz.

Definition at line 154 of file fsl_clock.c.

{
    return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
}

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CLOCK_GetCurSysClkConfig()

static void CLOCK_GetCurSysClkConfig ( scg_sys_clk_config_t *  config )

inlinestatic

Gets the system clock configuration in the current power mode.

This function gets the system configuration in the current power mode.

Parameters

config

Pointer to the configuration.

Definition at line 823 of file fsl_clock.h.

{
    assert(config);
 
    *(uint32_t *)config = SCG->CSR;
}

Referenced by CLOCK_CONFIG_FircSafeConfig(), CLOCK_GetSysClkFreq(), and setClockConfig().

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CLOCK_GetErClkFreq()

uint32_t CLOCK_GetErClkFreq

(

void

)

Get the external reference clock frequency (ERCLK).

Returns

Clock frequency in Hz.

brief Get the external reference clock frequency (ERCLK).

return Clock frequency in Hz.

Definition at line 104 of file fsl_clock.c.

{
    if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCEN_MASK)
    {
        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
        assert(g_xtal0Freq);
        return g_xtal0Freq;
    }
    else
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq().

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CLOCK_GetFircAsyncFreq()

uint32_t CLOCK_GetFircAsyncFreq

(

scg_async_clk_t

type

)

Gets the SCG asynchronous clock frequency from the FIRC.

Parameters

type	The asynchronous clock type.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG asynchronous clock frequency from the FIRC.

param type The asynchronous clock type. return Clock frequency; If the clock is invalid, returns 0.

Definition at line 803 of file fsl_clock.c.

{
    uint32_t fircFreq = CLOCK_GetFircFreq();
    uint32_t divider = 0U;
 
    /* Get divider. */
    if (fircFreq)
    {
        switch (type)
        {
            case kSCG_AsyncDiv2Clk: /* FIRCDIV2_CLK. */
                divider = SCG_FIRCDIV_FIRCDIV2_VAL;
                break;
            case kSCG_AsyncDiv1Clk: /* FIRCDIV1_CLK. */
                divider = SCG_FIRCDIV_FIRCDIV1_VAL;
                break;
            default:
                break;
        }
    }
    if (divider)
    {
        return fircFreq >> (divider - 1U);
    }
    else /* Output disabled. */
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), and CLOCK_GetIpFreq().

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CLOCK_GetFircFreq()

uint32_t CLOCK_GetFircFreq

(

void

)

Gets the SCG FIRC clock frequency.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG FIRC clock frequency.

return Clock frequency; If the clock is invalid, returns 0.

Definition at line 781 of file fsl_clock.c.

{
    static const uint32_t fircFreq[] = {
        SCG_FIRC_FREQ0, SCG_FIRC_FREQ1, SCG_FIRC_FREQ2, SCG_FIRC_FREQ3,
    };
 
    if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is valid. */
    {
        return fircFreq[SCG_FIRCCFG_RANGE_VAL];
    }
    else
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFircAsyncFreq(), CLOCK_GetFreq(), CLOCK_GetSysClkFreq(), and CLOCK_GetSysPllCommonFreq().

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CLOCK_GetFlashClkFreq()

uint32_t CLOCK_GetFlashClkFreq

(

void

)

Get the flash clock frequency.

Returns

Clock frequency in Hz.

brief Get the flash clock frequency.

return Clock frequency in Hz.

Definition at line 134 of file fsl_clock.c.

{
    return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
}

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CLOCK_GetFreq()

uint32_t CLOCK_GetFreq

(

clock_name_t

clockName

)

Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

Parameters

clockName

Clock names defined in clock_name_t

Returns

Clock frequency value in hertz

brief Gets the clock frequency for a specific clock name.

This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t.

param clockName Clock names defined in clock_name_t return Clock frequency value in hertz

Definition at line 168 of file fsl_clock.c.

{
    uint32_t freq;
 
    switch (clockName)
    {
        case kCLOCK_CoreSysClk:
            freq = CLOCK_GetSysClkFreq(kSCG_SysClkCore);
            break;
        case kCLOCK_BusClk:
            freq = CLOCK_GetSysClkFreq(kSCG_SysClkBus);
            break;
        case kCLOCK_FlashClk:
            freq = CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
            break;
 
        case kCLOCK_ScgSysOscClk:
            freq = CLOCK_GetSysOscFreq();
            break;
        case kCLOCK_ScgSircClk:
            freq = CLOCK_GetSircFreq();
            break;
        case kCLOCK_ScgFircClk:
            freq = CLOCK_GetFircFreq();
            break;
        case kCLOCK_ScgSysPllClk:
            freq = CLOCK_GetSysPllFreq();
            break;
 
        case kCLOCK_ScgSysOscAsyncDiv1Clk:
            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv1Clk);
            break;
        case kCLOCK_ScgSysOscAsyncDiv2Clk:
            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv2Clk);
            break;
 
        case kCLOCK_ScgSircAsyncDiv1Clk:
            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv1Clk);
            break;
        case kCLOCK_ScgSircAsyncDiv2Clk:
            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv2Clk);
            break;
 
        case kCLOCK_ScgFircAsyncDiv1Clk:
            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv1Clk);
            break;
        case kCLOCK_ScgFircAsyncDiv2Clk:
            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv2Clk);
            break;
 
        case kCLOCK_ScgSysPllAsyncDiv1Clk:
            freq = CLOCK_GetSysPllAsyncFreq(kSCG_AsyncDiv1Clk);
            break;
        case kCLOCK_ScgSysPllAsyncDiv2Clk:
            freq = CLOCK_GetSysPllAsyncFreq(kSCG_AsyncDiv2Clk);
            break;
 
        case kCLOCK_LpoClk:
            freq = LPO_CLK_FREQ;
            break;
        case kCLOCK_Osc32kClk:
            freq = CLOCK_GetOsc32kClkFreq();
            break;
        case kCLOCK_ErClk:
            freq = CLOCK_GetErClkFreq();
            break;
        default:
            freq = 0U;
            break;
    }
    return freq;
}

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CLOCK_GetIpFreq()

uint32_t CLOCK_GetIpFreq

(

clock_ip_name_t

name

)

Gets the clock frequency for a specific IP module.

This function gets the IP module clock frequency based on PCC registers. It is only used for the IP modules which could select clock source by PCC[PCS].

Parameters

name	Which peripheral to get, see clock_ip_name_t.

Returns

Clock frequency value in hertz

brief Gets the clock frequency for a specific IP module.

This function gets the IP module clock frequency based on PCC registers. It is only used for the IP modules which could select clock source by PCC[PCS].

param name Which peripheral to get, see clock_ip_name_t. return Clock frequency value in hertz

Definition at line 250 of file fsl_clock.c.

{
    uint32_t reg = (*(volatile uint32_t *)name);
 
    scg_async_clk_t asycClk;
    uint32_t freq;
 
    assert(reg & PCC_CLKCFG_PR_MASK);
 
    /* FTM uses SCG DIV1 clock, others use SCG DIV2 clock. */
    if ((kCLOCK_Ftm0 == name) || (kCLOCK_Ftm1 == name) || (kCLOCK_Ftm2 == name) || (kCLOCK_Ftm3 == name))
    {
        asycClk = kSCG_AsyncDiv1Clk;
    }
    else
    {
        asycClk = kSCG_AsyncDiv2Clk;
    }
 
    switch (PCC_PCS_VAL(reg))
    {
        case kCLOCK_IpSrcSysOscAsync:
            freq = CLOCK_GetSysOscAsyncFreq(asycClk);
            break;
        case kCLOCK_IpSrcSircAsync:
            freq = CLOCK_GetSircAsyncFreq(asycClk);
            break;
        case kCLOCK_IpSrcFircAsync:
            freq = CLOCK_GetFircAsyncFreq(asycClk);
            break;
        case kCLOCK_IpSrcSysPllAsync:
            freq = CLOCK_GetSysPllAsyncFreq(asycClk);
            break;
        default:
            freq = 0U;
            break;
    }
 
    return freq;
}

Referenced by spi_lld_start().

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CLOCK_GetOsc32kClkFreq()

uint32_t CLOCK_GetOsc32kClkFreq

(

void

)

Get the OSC 32K clock frequency (OSC32KCLK).

Returns

Clock frequency in Hz.

brief Get the OSC 32K clock frequency (OSC32KCLK).

return Clock frequency in Hz.

Definition at line 123 of file fsl_clock.c.

{
    assert(g_xtal32Freq);
    return g_xtal32Freq;
}

Referenced by CLOCK_GetFreq().

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CLOCK_GetSircAsyncFreq()

uint32_t CLOCK_GetSircAsyncFreq

(

scg_async_clk_t

type

)

Gets the SCG asynchronous clock frequency from the SIRC.

Parameters

type	The asynchronous clock type.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG asynchronous clock frequency from the SIRC.

param type The asynchronous clock type. return Clock frequency; If the clock is invalid, returns 0.

Definition at line 647 of file fsl_clock.c.

{
    uint32_t sircFreq = CLOCK_GetSircFreq();
    uint32_t divider = 0U;
 
    /* Get divider. */
    if (sircFreq)
    {
        switch (type)
        {
            case kSCG_AsyncDiv2Clk: /* SIRCDIV2_CLK. */
                divider = SCG_SIRCDIV_SIRCDIV2_VAL;
                break;
            case kSCG_AsyncDiv1Clk: /* SIRCDIV2_CLK. */
                divider = SCG_SIRCDIV_SIRCDIV1_VAL;
                break;
            default:
                break;
        }
    }
    if (divider)
    {
        return sircFreq >> (divider - 1U);
    }
    else /* Output disabled. */
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), and CLOCK_GetIpFreq().

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CLOCK_GetSircFreq()

uint32_t CLOCK_GetSircFreq

(

void

)

Gets the SCG SIRC clock frequency.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG SIRC clock frequency.

return Clock frequency; If the clock is invalid, returns 0.

Definition at line 627 of file fsl_clock.c.

{
    static const uint32_t sircFreq[] = {SCG_SIRC_LOW_RANGE_FREQ, SCG_SIRC_HIGH_RANGE_FREQ};
 
    if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */
    {
        return sircFreq[SCG_SIRCCFG_RANGE_VAL];
    }
    else
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), CLOCK_GetSircAsyncFreq(), and CLOCK_GetSysClkFreq().

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CLOCK_GetSysClkFreq()

uint32_t CLOCK_GetSysClkFreq

(

scg_sys_clk_t

type

)

Gets the SCG system clock frequency.

This function gets the SCG system clock frequency. These clocks are used for core, platform, external, and bus clock domains.

Parameters

type	Which type of clock to get, core clock or slow clock.

Returns

Clock frequency.

brief Gets the SCG system clock frequency.

This function gets the SCG system clock frequency. These clocks are used for core, platform, external, and bus clock domains.

param type Which type of clock to get, core clock or slow clock. return Clock frequency.

Definition at line 339 of file fsl_clock.c.

{
    uint32_t freq;
 
    scg_sys_clk_config_t sysClkConfig;
 
    CLOCK_GetCurSysClkConfig(&sysClkConfig);
 
    switch (sysClkConfig.src)
    {
        case kSCG_SysClkSrcSysOsc:
            freq = CLOCK_GetSysOscFreq();
            break;
        case kSCG_SysClkSrcSirc:
            freq = CLOCK_GetSircFreq();
            break;
        case kSCG_SysClkSrcFirc:
            freq = CLOCK_GetFircFreq();
            break;
        case kSCG_SysClkSrcSysPll:
            freq = CLOCK_GetSysPllFreq();
            break;
        default:
            freq = 0U;
            break;
    }
 
    freq /= (sysClkConfig.divCore + 1U);
 
    if (kSCG_SysClkSlow == type)
    {
        freq /= (sysClkConfig.divSlow + 1U);
    }
    else if (kSCG_SysClkBus == type)
    {
        freq /= (sysClkConfig.divBus + 1U);
    }
    else
    {
    }
 
    return freq;
}

Referenced by CLOCK_GetBusClkFreq(), CLOCK_GetCoreSysClkFreq(), CLOCK_GetFlashClkFreq(), and CLOCK_GetFreq().

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CLOCK_GetSysOscAsyncFreq()

uint32_t CLOCK_GetSysOscAsyncFreq

(

scg_async_clk_t

type

)

Gets the SCG asynchronous clock frequency from the system OSC.

Parameters

type	The asynchronous clock type.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG asynchronous clock frequency from the system OSC.

param type The asynchronous clock type. return Clock frequency; If the clock is invalid, returns 0.

Definition at line 514 of file fsl_clock.c.

{
    uint32_t oscFreq = CLOCK_GetSysOscFreq();
    uint32_t divider = 0U;
 
    /* Get divider. */
    if (oscFreq)
    {
        switch (type)
        {
            case kSCG_AsyncDiv2Clk: /* SOSCDIV2_CLK. */
                divider = SCG_SOSCDIV_SOSCDIV2_VAL;
                break;
            case kSCG_AsyncDiv1Clk: /* SOSCDIV1_CLK. */
                divider = SCG_SOSCDIV_SOSCDIV1_VAL;
                break;
            default:
                break;
        }
    }
    if (divider)
    {
        return oscFreq >> (divider - 1U);
    }
    else /* Output disabled. */
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), and CLOCK_GetIpFreq().

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CLOCK_GetSysOscFreq()

uint32_t CLOCK_GetSysOscFreq

(

void

)

Gets the SCG system OSC clock frequency (SYSOSC).

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG system OSC clock frequency (SYSOSC).

return Clock frequency; If the clock is invalid, returns 0.

Definition at line 494 of file fsl_clock.c.

{
    if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */
    {
        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
        assert(g_xtal0Freq);
        return g_xtal0Freq;
    }
    else
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), CLOCK_GetSysClkFreq(), CLOCK_GetSysOscAsyncFreq(), and CLOCK_GetSysPllCommonFreq().

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CLOCK_GetSysPllAsyncFreq()

uint32_t CLOCK_GetSysPllAsyncFreq

(

scg_async_clk_t

type

)

Gets the SCG asynchronous clock frequency from the system PLL.

Parameters

type	The asynchronous clock type.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG asynchronous clock frequency from the system PLL.

param type The asynchronous clock type. return Clock frequency; If the clock is invalid, returns 0.

Definition at line 1102 of file fsl_clock.c.

{
    uint32_t pllFreq = CLOCK_GetSysPllFreq();
    uint32_t divider = 0U;
 
    /* Get divider. */
    if (pllFreq)
    {
        switch (type)
        {
            case kSCG_AsyncDiv2Clk: /* SPLLDIV2_CLK. */
                divider = SCG_SPLLDIV_SPLLDIV2_VAL;
                break;
            case kSCG_AsyncDiv1Clk: /* SPLLDIV1_CLK. */
                divider = SCG_SPLLDIV_SPLLDIV1_VAL;
                break;
            default:
                break;
        }
    }
    if (divider)
    {
        return pllFreq >> (divider - 1U);
    }
    else /* Output disabled. */
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), and CLOCK_GetIpFreq().

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CLOCK_GetSysPllFreq()

uint32_t CLOCK_GetSysPllFreq

(

void

)

Gets the SCG system PLL clock frequency.

Returns

Clock frequency; If the clock is invalid, returns 0.

brief Gets the SCG system PLL clock frequency.

return Clock frequency; If the clock is invalid, returns 0.

Definition at line 1080 of file fsl_clock.c.

{
    uint32_t freq;
 
    if (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) /* System PLL is valid. */
    {
        freq = CLOCK_GetSysPllCommonFreq();
 
        return freq >> 1U;
    }
    else
    {
        return 0U;
    }
}

Referenced by CLOCK_GetFreq(), CLOCK_GetSysClkFreq(), and CLOCK_GetSysPllAsyncFreq().

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CLOCK_GetSysPllMultDiv()

uint32_t CLOCK_GetSysPllMultDiv	(	uint32_t	refFreq,
		uint32_t	desireFreq,
		uint8_t *	mult,
		uint8_t *	prediv
	)

Calculates the MULT and PREDIV for the PLL.

This function calculates the proper MULT and PREDIV to generate the desired PLL output frequency with the input reference clock frequency. It returns the closest frequency match that the PLL can generate. The corresponding MULT/PREDIV are returned with parameters. If the desired frequency is not valid, this function returns 0.

Parameters

refFreq	The input reference clock frequency.
desireFreq	The desired output clock frequency.
mult	The value of MULT.
prediv	The value of PREDIV.

Returns

The PLL output frequency with the MULT and PREDIV; If the desired frequency can't be generated, this function returns 0U.

brief Calculates the MULT and PREDIV for the PLL.

This function calculates the proper MULT and PREDIV to generate the desired PLL output frequency with the input reference clock frequency. It returns the closest frequency match that the PLL can generate. The corresponding MULT/PREDIV are returned with parameters. If the desired frequency is not valid, this function returns 0.

param refFreq The input reference clock frequency. param desireFreq The desired output clock frequency. param mult The value of MULT. param prediv The value of PREDIV. return The PLL output frequency with the MULT and PREDIV; If the desired frequency can't be generated, this function returns 0U.

Definition at line 848 of file fsl_clock.c.

{
    uint8_t ret_prediv;          /* PREDIV to return */
    uint8_t ret_mult;            /* MULT to return */
    uint8_t prediv_min;          /* Minimal PREDIV value to make reference clock in allowed range. */
    uint8_t prediv_max;          /* Max PREDIV value to make reference clock in allowed range. */
    uint8_t prediv_cur;          /* PREDIV value for iteration. */
    uint8_t mult_cur;            /* MULT value for iteration. */
    uint32_t ret_freq = 0U;      /* Output frequency to return .*/
    uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */
    uint32_t ref_div;            /* Reference frequency after PREDIV. */
 
    /*
     * Steps:
     * 1. Get allowed prediv with such rules:
     *    1). refFreq / prediv >= SCG_PLL_REF_MIN.
     *    2). refFreq / prediv <= SCG_PLL_REF_MAX.
     * 2. For each allowed prediv, there are two candidate mult values:
     *    1). (desireFreq / (refFreq / prediv)).
     *    2). (desireFreq / (refFreq / prediv)) + 1.
     *    If could get the precise desired frequency, return current prediv and
     *    mult directly. Otherwise choose the one which is closer to desired
     *    frequency.
     */
 
    /* Reference frequency is out of range. */
    if ((refFreq < SCG_SPLL_REF_MIN) ||
        (refFreq > (SCG_SPLL_REF_MAX * (SCG_SPLL_PREDIV_MAX_VALUE + SCG_SPLL_PREDIV_BASE_VALUE))))
    {
        return 0U;
    }
 
    /* refFreq/PREDIV must in a range. First get the allowed PREDIV range. */
    prediv_max = refFreq / SCG_SPLL_REF_MIN;
    prediv_min = (refFreq + SCG_SPLL_REF_MAX - 1U) / SCG_SPLL_REF_MAX;
 
    desireFreq *= 2U;
 
    /* PREDIV traversal. */
    for (prediv_cur = prediv_max; prediv_cur >= prediv_min; prediv_cur--)
    {
        /*
         * For each PREDIV, the available MULT is (desireFreq*PREDIV/refFreq)
         * or (desireFreq*PREDIV/refFreq + 1U). This function chooses the closer
         * one.
         */
        /* Reference frequency after PREDIV. */
        ref_div = refFreq / prediv_cur;
 
        mult_cur = desireFreq / ref_div;
 
        if ((mult_cur < SCG_SPLL_MULT_BASE_VALUE - 1U) ||
            (mult_cur > SCG_SPLL_MULT_BASE_VALUE + SCG_SPLL_MULT_MAX_VALUE))
        {
            /* No MULT is available with this PREDIV. */
            continue;
        }
 
        ret_freq = mult_cur * ref_div;
 
        if (mult_cur >= SCG_SPLL_MULT_BASE_VALUE)
        {
            if (ret_freq == desireFreq) /* If desire frequency is got. */
            {
                *prediv = prediv_cur - SCG_SPLL_PREDIV_BASE_VALUE;
                *mult = mult_cur - SCG_SPLL_MULT_BASE_VALUE;
                return ret_freq / 2U;
            }
            if (diff > desireFreq - ret_freq) /* New PRDIV/VDIV is closer. */
            {
                diff = desireFreq - ret_freq;
                ret_prediv = prediv_cur;
                ret_mult = mult_cur;
            }
        }
        mult_cur++;
        if (mult_cur <= (SCG_SPLL_MULT_BASE_VALUE + SCG_SPLL_MULT_MAX_VALUE))
        {
            ret_freq += ref_div;
            if (diff > ret_freq - desireFreq) /* New PRDIV/VDIV is closer. */
            {
                diff = ret_freq - desireFreq;
                ret_prediv = prediv_cur;
                ret_mult = mult_cur;
            }
        }
    }
 
    if (0xFFFFFFFFU != diff)
    {
        /* PREDIV/MULT found. */
        *prediv = ret_prediv - SCG_SPLL_PREDIV_BASE_VALUE;
        *mult = ret_mult - SCG_SPLL_MULT_BASE_VALUE;
        return ((refFreq / ret_prediv) * ret_mult) / 2;
    }
    else
    {
        return 0U; /* No proper PREDIV/MULT found. */
    }
}

CLOCK_InitFirc()

status_t CLOCK_InitFirc

(

const scg_firc_config_t *

config

)

Initializes the SCG fast IRC clock.

This function enables the SCG fast IRC clock according to the configuration.

Parameters

config

Pointer to the configuration structure.

Return values

kStatus_Success	FIRC is initialized.
kStatus_SCG_Busy	FIRC has been enabled and is used by the system clock.
kStatus_ReadOnly	FIRC control register is locked.

Note

This function can't detect whether the FIRC has been enabled and used by an IP.

brief Initializes the SCG fast IRC clock.

This function enables the SCG fast IRC clock according to the configuration.

param config Pointer to the configuration structure. retval kStatus_Success FIRC is initialized. retval kStatus_SCG_Busy FIRC has been enabled and is used by the system clock. retval kStatus_ReadOnly FIRC control register is locked.

note This function can't detect whether the FIRC has been enabled and used by an IP.

Definition at line 690 of file fsl_clock.c.

{
    assert(config);
 
    status_t status;
 
    /* De-init the FIRC first. */
    status = CLOCK_DeinitFirc();
 
    if (kStatus_Success != status)
    {
        return status;
    }
 
    /* Now start to set up FIRC clock. */
    /* Step 1. Setup dividers. */
    SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2);
 
    /* Step 2. Set FIRC configuration. */
    SCG->FIRCCFG = SCG_FIRCCFG_RANGE(config->range);
 
    /* Step 3. Set trimming configuration. */
    if (config->trimConfig)
    {
        SCG->FIRCTCFG =
            SCG_FIRCTCFG_TRIMDIV(config->trimConfig->trimDiv) | SCG_FIRCTCFG_TRIMSRC(config->trimConfig->trimSrc);
 
        /* TODO: Write FIRCSTAT cause bus error: TKT266932. */
        if (kSCG_FircTrimNonUpdate == config->trimConfig->trimMode)
        {
            SCG->FIRCSTAT = SCG_FIRCSTAT_TRIMCOAR(config->trimConfig->trimCoar) |
                            SCG_FIRCSTAT_TRIMFINE(config->trimConfig->trimFine);
        }
 
        /* trim mode. */
        SCG->FIRCCSR = config->trimConfig->trimMode;
 
        if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK)
        {
            return kStatus_Fail;
        }
    }
 
    /* Step 4. Enable clock. */
    SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | config->enableMode);
 
    /* Step 5. Wait for FIRC clock to be valid. */
    while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
    {
    }
 
    return kStatus_Success;
}

Referenced by CLOCK_CONFIG_FircSafeConfig().

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CLOCK_InitSirc()

status_t CLOCK_InitSirc

(

const scg_sirc_config_t *

config

)

Initializes the SCG slow IRC clock.

This function enables the SCG slow IRC clock according to the configuration.

Parameters

config

Pointer to the configuration structure.

Return values

kStatus_Success	SIRC is initialized.
kStatus_SCG_Busy	SIRC has been enabled and is used by system clock.
kStatus_ReadOnly	SIRC control register is locked.

Note

This function can't detect whether the system OSC has been enabled and used by an IP.

brief Initializes the SCG slow IRC clock.

This function enables the SCG slow IRC clock according to the configuration.

param config Pointer to the configuration structure. retval kStatus_Success SIRC is initialized. retval kStatus_SCG_Busy SIRC has been enabled and is used by system clock. retval kStatus_ReadOnly SIRC control register is locked.

note This function can't detect whether the system OSC has been enabled and used by an IP.

Definition at line 558 of file fsl_clock.c.

{
    assert(config);
 
    status_t status;
 
    /* De-init the SIRC first. */
    status = CLOCK_DeinitSirc();
 
    if (kStatus_Success != status)
    {
        return status;
    }
 
    /* Now start to set up SIRC clock. */
    /* Step 1. Setup dividers. */
    SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2);
 
    /* Step 2. Set SIRC configuration. */
    SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range);
 
    /* Step 3. Enable clock. */
    SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode;
 
    /* Step 4. Wait for SIRC clock to be valid. */
    while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK))
    {
    }
 
    return kStatus_Success;
}

Referenced by CLOCK_CONFIG_FircSafeConfig().

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CLOCK_InitSysOsc()

status_t CLOCK_InitSysOsc

(

const scg_sosc_config_t *

config

)

Initializes the SCG system OSC.

This function enables the SCG system OSC clock according to the configuration.

Parameters

config

Pointer to the configuration structure.

Return values

kStatus_Success	System OSC is initialized.
kStatus_SCG_Busy	System OSC has been enabled and is used by the system clock.
kStatus_ReadOnly	System OSC control register is locked.

Note

This function can't detect whether the system OSC has been enabled and used by an IP.

brief Initializes the SCG system OSC.

This function enables the SCG system OSC clock according to the configuration.

param config Pointer to the configuration structure. retval kStatus_Success System OSC is initialized. retval kStatus_SCG_Busy System OSC has been enabled and is used by the system clock. retval kStatus_ReadOnly System OSC control register is locked.

note This function can't detect whether the system OSC has been enabled and used by an IP.

Definition at line 397 of file fsl_clock.c.

{
    assert(config);
    uint8_t range = 0U; /* SCG_SOSCCFG[RANGE] */
    status_t status;
    uint8_t tmp8;
 
    /* If crystal oscillator used, need to get RANGE value base on frequency. */
    if (kSCG_SysOscModeExt != config->workMode)
    {
        if ((config->freq >= 32768U) && (config->freq <= 40000U))
        {
            range = 1U;
        }
        else if ((config->freq >= 1000000U) && (config->freq <= 8000000U))
        {
            range = 2U;
        }
        else if ((config->freq >= 8000000U) && (config->freq <= 32000000U))
        {
            range = 3U;
        }
        else
        {
            return kStatus_InvalidArgument;
        }
    }
 
    /* De-init the SOSC first. */
    status = CLOCK_DeinitSysOsc();
 
    if (kStatus_Success != status)
    {
        return status;
    }
 
    /* Now start to set up OSC clock. */
    /* Step 1. Setup dividers. */
    SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2);
 
    /* Step 2. Set OSC configuration. */
    SCG->SOSCCFG = config->workMode | SCG_SOSCCFG_RANGE(range);
 
    /* Step 3. Enable clock. */
    /* SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK | (config->enableMode); */
    tmp8 = config->enableMode;
    tmp8 |= SCG_SOSCCSR_SOSCEN_MASK;
    SCG->SOSCCSR = tmp8;
 
    /* Step 4. Wait for OSC clock to be valid. */
    while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
    {
    }
 
    /* Step 5. Enabe monitor. */
    SCG->SOSCCSR |= (uint32_t)config->monitorMode;
 
    return kStatus_Success;
}

Referenced by ke1xf_clock_init().

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CLOCK_InitSysPll()

status_t CLOCK_InitSysPll

(

const scg_spll_config_t *

config

)

Initializes the SCG system PLL.

This function enables the SCG system PLL clock according to the configuration. The system PLL can use the system OSC or FIRC as the clock source. Ensure that the source clock is valid before calling this function.

Example code for initializing SPLL clock output:

const scg_spll_config_t g_scgSysPllConfig = {.enableMode = kSCG_SysPllEnable,
                                           .monitorMode = kSCG_SysPllMonitorDisable,
                                           .div1 = kSCG_AsyncClkDivBy1,
                                           .div2 = kSCG_AsyncClkDisable,
                                           .div3 = kSCG_AsyncClkDivBy2,
                                           .src = kSCG_SysPllSrcFirc,
                                           .isBypassSelected = false,
                                           .isPfdSelected = false, // Configure SPLL PFD as diabled
                                           .prediv = 5U,
                                           .pfdClkout = kSCG_AuxPllPfd0Clk, // No need to configure pfdClkout; only
needed for initialization
                                           .mult = 20U,
                                           .pllPostdiv1 = kSCG_SysClkDivBy3,
                                           .pllPostdiv2 = kSCG_SysClkDivBy4};
CLOCK_InitSysPll(&g_scgSysPllConfig);

Parameters

config

Pointer to the configuration structure.

Return values

kStatus_Success	System PLL is initialized.
kStatus_SCG_Busy	System PLL has been enabled and is used by the system clock.
kStatus_ReadOnly	System PLL control register is locked.

Note

This function can't detect whether the system PLL has been enabled and used by an IP.

brief Initializes the SCG system PLL.

This function enables the SCG system PLL clock according to the configuration. The system PLL can use the system OSC or FIRC as the clock source. Ensure that the source clock is valid before calling this function.

Example code for initializing SPLL clock output: code const scg_spll_config_t g_scgSysPllConfig = {.enableMode = kSCG_SysPllEnable, .monitorMode = kSCG_SysPllMonitorDisable, .div1 = kSCG_AsyncClkDivBy1, .div2 = kSCG_AsyncClkDisable, .div3 = kSCG_AsyncClkDivBy2, .src = kSCG_SysPllSrcFirc, .isBypassSelected = false, .isPfdSelected = false, // Configure SPLL PFD as diabled .prediv = 5U, .pfdClkout = kSCG_AuxPllPfd0Clk, // No need to configure pfdClkout; only needed for initialization .mult = 20U, .pllPostdiv1 = kSCG_SysClkDivBy3, .pllPostdiv2 = kSCG_SysClkDivBy4}; CLOCK_InitSysPll(&g_scgSysPllConfig); endcode

param config Pointer to the configuration structure. retval kStatus_Success System PLL is initialized. retval kStatus_SCG_Busy System PLL has been enabled and is used by the system clock. retval kStatus_ReadOnly System PLL control register is locked.

note This function can't detect whether the system PLL has been enabled and used by an IP.

Definition at line 984 of file fsl_clock.c.

{
    assert(config);
 
    status_t status;
 
    /* De-init the SPLL first. */
    status = CLOCK_DeinitSysPll();
 
    if (kStatus_Success != status)
    {
        return status;
    }
 
    /* Now start to set up PLL clock. */
    /* Step 1. Setup dividers. */
    SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) | SCG_SPLLDIV_SPLLDIV2(config->div2);
 
    /* Step 2. Set PLL configuration. */
    SCG->SPLLCFG =
        SCG_SPLLCFG_SOURCE(config->src) | SCG_SPLLCFG_PREDIV(config->prediv) | SCG_SPLLCFG_MULT(config->mult);
 
    /* Step 3. Enable clock. */
    SCG->SPLLCSR = SCG_SPLLCSR_SPLLEN_MASK | config->enableMode;
 
    /* Step 4. Wait for PLL clock to be valid. */
    while (!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK))
    {
    }
 
    /* Step 5. Enabe monitor. */
    SCG->SPLLCSR |= (uint32_t)config->monitorMode;
 
    return kStatus_Success;
}

Referenced by ke1xf_clock_init().

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CLOCK_IsEnabledByOtherCore()

static bool CLOCK_IsEnabledByOtherCore ( clock_ip_name_t  name )

inlinestatic

Check whether the clock is already enabled and configured by any other core.

Parameters

name	Which peripheral to check, see clock_ip_name_t.

Returns

True if clock is already enabled, otherwise false.

Definition at line 667 of file fsl_clock.h.

{
    assert((*(volatile uint32_t *)name) & PCC_CLKCFG_PR_MASK);
 
    return ((*(volatile uint32_t *)name) & PCC_CLKCFG_INUSE_MASK) ? true : false;
}

CLOCK_IsFircErr()

static bool CLOCK_IsFircErr ( void  )

inlinestatic

Checks whether the FIRC clock error occurs.

Returns

True if the error occurs, false if not.

Definition at line 1132 of file fsl_clock.h.

{
    return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK);
}

CLOCK_IsFircValid()

static bool CLOCK_IsFircValid ( void  )

inlinestatic

Checks whether the FIRC clock is valid.

Returns

True if clock is valid, false if not.

Definition at line 1150 of file fsl_clock.h.

{
    return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK);
}

CLOCK_IsSircValid()

static bool CLOCK_IsSircValid ( void  )

inlinestatic

Checks whether the SIRC clock is valid.

Returns

True if clock is valid, false if not.

Definition at line 1047 of file fsl_clock.h.

{
    return (bool)(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK);
}

CLOCK_IsSysOscErr()

static bool CLOCK_IsSysOscErr ( void  )

inlinestatic

Checks whether the system OSC clock error occurs.

Returns

True if the error occurs, false if not.

Definition at line 924 of file fsl_clock.h.

{
    return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCERR_MASK);
}

CLOCK_IsSysOscValid()

static bool CLOCK_IsSysOscValid ( void  )

inlinestatic

Checks whether the system OSC clock is valid.

Returns

True if clock is valid, false if not.

Definition at line 961 of file fsl_clock.h.

{
    return (bool)(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK);
}

CLOCK_IsSysPllErr()

static bool CLOCK_IsSysPllErr ( void  )

inlinestatic

Checks whether the system PLL clock error occurs.

Returns

True if an error occurs, false if not.

Definition at line 1274 of file fsl_clock.h.

{
    return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLERR_MASK);
}

CLOCK_IsSysPllValid()

static bool CLOCK_IsSysPllValid ( void  )

inlinestatic

Checks whether the system PLL clock is valid.

Returns

True if the clock is valid, false if not.

Definition at line 1311 of file fsl_clock.h.

{
    return (bool)(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK);
}

CLOCK_SetClkOutSel()

static void CLOCK_SetClkOutSel ( clock_clkout_src_t  setting )

inlinestatic

Sets the clock out selection.

This function sets the clock out selection (CLKOUTSEL).

Parameters

setting

The selection to set.

Returns

The current clock out selection.

Definition at line 838 of file fsl_clock.h.

{
    SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
}

CLOCK_SetFircAsyncClkDiv()

static void CLOCK_SetFircAsyncClkDiv ( scg_async_clk_t  asyncClk, scg_async_clk_div_t  divider  )

inlinestatic

Set the asynchronous clock divider.

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note

There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

Definition at line 1095 of file fsl_clock.h.

{
    uint32_t reg = SCG->FIRCDIV;
 
    switch (asyncClk)
    {
        case kSCG_AsyncDiv2Clk:
            reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider);
            break;
        default:
            reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider);
            break;
    }
 
    SCG->FIRCDIV = reg;
}

CLOCK_SetHsrunModeSysClkConfig()

static void CLOCK_SetHsrunModeSysClkConfig ( const scg_sys_clk_config_t *  config )

inlinestatic

Sets the system clock configuration for HSRUN mode.

This function sets the system clock configuration for HSRUN mode.

Parameters

config

Pointer to the configuration.

Definition at line 809 of file fsl_clock.h.

{
    assert(config);
 
    SCG->HCCR = *(const uint32_t *)config;
}

Referenced by setClockConfig().

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CLOCK_SetIpSrc()

static void CLOCK_SetIpSrc ( clock_ip_name_t  name, clock_ip_src_t  src  )

inlinestatic

Set the clock source for specific IP module.

Set the clock source for specific IP, not all modules need to set the clock source, should only use this function for the modules need source setting.

Parameters

name	Which peripheral to check, see clock_ip_name_t.
src	Clock source to set.

Definition at line 684 of file fsl_clock.h.

{
    uint32_t reg = (*(volatile uint32_t *)name);
 
    assert(reg & PCC_CLKCFG_PR_MASK);
    assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other core. */
 
    reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src);
 
    /*
     * If clock is already enabled, first disable it, then set the clock
     * source and re-enable it.
     */
    (*(volatile uint32_t *)name) = reg & ~PCC_CLKCFG_CGC_MASK;
    (*(volatile uint32_t *)name) = reg;
}

Referenced by ke1xf_clock_init().

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CLOCK_SetRunModeSysClkConfig()

static void CLOCK_SetRunModeSysClkConfig ( const scg_sys_clk_config_t *  config )

inlinestatic

Sets the system clock configuration for RUN mode.

This function sets the system clock configuration for RUN mode.

Parameters

config

Pointer to the configuration.

Definition at line 795 of file fsl_clock.h.

{
    assert(config);
 
    SCG->RCCR = *(const uint32_t *)config;
}

Referenced by CLOCK_CONFIG_FircSafeConfig(), and setClockConfig().

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CLOCK_SetSircAsyncClkDiv()

static void CLOCK_SetSircAsyncClkDiv ( scg_async_clk_t  asyncClk, scg_async_clk_div_t  divider  )

inlinestatic

Set the asynchronous clock divider.

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note

There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

Definition at line 1010 of file fsl_clock.h.

{
    uint32_t reg = SCG->SIRCDIV;
 
    switch (asyncClk)
    {
        case kSCG_AsyncDiv2Clk:
            reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider);
            break;
        default:
            reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider);
            break;
    }
 
    SCG->SIRCDIV = reg;
}

CLOCK_SetSysOscAsyncClkDiv()

static void CLOCK_SetSysOscAsyncClkDiv ( scg_async_clk_t  asyncClk, scg_async_clk_div_t  divider  )

inlinestatic

Set the asynchronous clock divider.

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note

There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

Definition at line 887 of file fsl_clock.h.

{
    uint32_t reg = SCG->SOSCDIV;
 
    switch (asyncClk)
    {
        case kSCG_AsyncDiv2Clk:
            reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider);
            break;
        default:
            reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider);
            break;
    }
 
    SCG->SOSCDIV = reg;
}

CLOCK_SetSysOscMonitorMode()

static void CLOCK_SetSysOscMonitorMode ( scg_sosc_monitor_mode_t  mode )

inlinestatic

Sets the system OSC monitor mode.

This function sets the system OSC monitor mode. The mode can be disabled, it can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

Definition at line 945 of file fsl_clock.h.

{
    uint32_t reg = SCG->SOSCCSR;
 
    reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
 
    reg |= (uint32_t)mode;
 
    SCG->SOSCCSR = reg;
}

CLOCK_SetSysPllAsyncClkDiv()

static void CLOCK_SetSysPllAsyncClkDiv ( scg_async_clk_t  asyncClk, scg_async_clk_div_t  divider  )

inlinestatic

Set the asynchronous clock divider.

Parameters

asyncClk	Which asynchronous clock to configure.
divider	The divider value to set.

Note

There might be glitch when changing the asynchronous divider, so make sure the asynchronous clock is not used while changing divider.

Definition at line 1237 of file fsl_clock.h.

{
    uint32_t reg = SCG->SPLLDIV;
 
    switch (asyncClk)
    {
        case kSCG_AsyncDiv2Clk:
            reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider);
            break;
        default:
            reg = (reg & ~SCG_SPLLDIV_SPLLDIV1_MASK) | SCG_SPLLDIV_SPLLDIV1(divider);
            break;
    }
 
    SCG->SPLLDIV = reg;
}

CLOCK_SetSysPllMonitorMode()

static void CLOCK_SetSysPllMonitorMode ( scg_spll_monitor_mode_t  mode )

inlinestatic

Sets the system PLL monitor mode.

This function sets the system PLL monitor mode. The mode can be disabled. It can generate an interrupt when the error is disabled, or reset when the error is detected.

Parameters

mode	Monitor mode to set.

Definition at line 1295 of file fsl_clock.h.

{
    uint32_t reg = SCG->SPLLCSR;
 
    reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);
 
    reg |= (uint32_t)mode;
 
    SCG->SPLLCSR = reg;
}

CLOCK_SetVlprModeSysClkConfig()

static void CLOCK_SetVlprModeSysClkConfig ( const scg_sys_clk_config_t *  config )

inlinestatic

Sets the system clock configuration for VLPR mode.

This function sets the system clock configuration for VLPR mode.

Parameters

config

Pointer to the configuration.

Definition at line 781 of file fsl_clock.h.

{
    assert(config);
 
    SCG->VCCR = *(const uint32_t *)config;
}

CLOCK_SetXtal0Freq()

static void CLOCK_SetXtal0Freq ( uint32_t  freq )

inlinestatic

Sets the XTAL0 frequency based on board settings.

Parameters

freq	The XTAL0/EXTAL0 input clock frequency in Hz.

Definition at line 1347 of file fsl_clock.h.

{
    g_xtal0Freq = freq;
}

Referenced by ke1xf_clock_init().

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CLOCK_SetXtal32Freq()

static void CLOCK_SetXtal32Freq ( uint32_t  freq )

inlinestatic

Sets the XTAL32 frequency based on board settings.

Parameters

freq	The XTAL32/EXTAL32 input clock frequency in Hz.

Definition at line 1357 of file fsl_clock.h.

{
    g_xtal32Freq = freq;
}

OSC32_Deinit()

void OSC32_Deinit

(

OSC32_Type *

base

)

Deinitializes OSC32.

Parameters

base	OSC32 peripheral base address.

brief Deinitializes OSC32.

param base OSC32 peripheral base address.

Definition at line 321 of file fsl_clock.c.

{
    /* Only support one instance now. */
    assert(OSC32 == base);
 
    base->CR = 0U;
    CLOCK_DisableClock(kCLOCK_RtcOsc0);
}

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OSC32_Init()

void OSC32_Init	(	OSC32_Type *	base,
		osc32_mode_t	mode
	)

Initializes OSC32.

Parameters

base	OSC32 peripheral base address.
mode	OSC32 work mode, see osc32_mode_t

brief Initializes OSC32.

param base OSC32 peripheral base address. param mode OSC32 work mode, see ref osc32_mode_t

Definition at line 297 of file fsl_clock.c.

{
    /* Only support one instance now. */
    assert(OSC32 == base);
 
    CLOCK_EnableClock(kCLOCK_RtcOsc0);
 
    /* Set work mode. */
    base->CR = (uint8_t)mode;
 
    if (mode & OSC32_CR_ROSCEREFS_MASK)
    {
        /* If use crystal mode, wait for stable. */
        while (!(base->CR & OSC32_CR_ROSCSTB_MASK))
        {
        }
    }
}

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Variable Documentation

__pad0__

uint32_t _scg_sys_clk_config::__pad0__

Reserved.

Definition at line 384 of file fsl_clock.h.

__pad1__

uint32_t _scg_sys_clk_config::__pad1__

Reserved.

Definition at line 385 of file fsl_clock.h.

__pad2__

uint32_t _scg_sys_clk_config::__pad2__

Reserved.

Definition at line 387 of file fsl_clock.h.

__pad3__

uint32_t _scg_sys_clk_config::__pad3__

reserved.

Definition at line 389 of file fsl_clock.h.

div1 [1/4]

scg_async_clk_div_t _scg_sosc_config::div1

SOSCDIV1 value.

Definition at line 465 of file fsl_clock.h.

div1 [2/4]

scg_async_clk_div_t _scg_sirc_config::div1

SIRCDIV1 value.

Definition at line 494 of file fsl_clock.h.

div1 [3/4]

scg_async_clk_div_t _scg_firc_config_t::div1

FIRCDIV1 value.

Definition at line 577 of file fsl_clock.h.

div1 [4/4]

scg_async_clk_div_t _scg_spll_config::div1

SPLLDIV1 value.

Definition at line 620 of file fsl_clock.h.

div2 [1/4]

scg_async_clk_div_t _scg_sosc_config::div2

SOSCDIV2 value.

Definition at line 466 of file fsl_clock.h.

div2 [2/4]

scg_async_clk_div_t _scg_sirc_config::div2

SIRCDIV2 value.

Definition at line 495 of file fsl_clock.h.

div2 [3/4]

scg_async_clk_div_t _scg_firc_config_t::div2

FIRCDIV2 value.

Definition at line 578 of file fsl_clock.h.

div2 [4/4]

scg_async_clk_div_t _scg_spll_config::div2

SPLLDIV2 value.

Definition at line 621 of file fsl_clock.h.

divBus

uint32_t _scg_sys_clk_config::divBus

Bus clock divider, see scg_sys_clk_div_t.

Definition at line 383 of file fsl_clock.h.

Referenced by CLOCK_GetSysClkFreq().

divCore

uint32_t _scg_sys_clk_config::divCore

Core clock divider, see scg_sys_clk_div_t.

Definition at line 386 of file fsl_clock.h.

Referenced by CLOCK_GetSysClkFreq().

divSlow

uint32_t _scg_sys_clk_config::divSlow

Slow clock divider, see scg_sys_clk_div_t.

Definition at line 382 of file fsl_clock.h.

Referenced by CLOCK_CONFIG_FircSafeConfig(), and CLOCK_GetSysClkFreq().

enableMode [1/4]

uint8_t _scg_sosc_config::enableMode

Enable mode, OR'ed value of _scg_sosc_enable_mode.

Definition at line 463 of file fsl_clock.h.

enableMode [2/4]

uint32_t _scg_sirc_config::enableMode

Enable mode, OR'ed value of _scg_sirc_enable_mode.

Definition at line 493 of file fsl_clock.h.

Referenced by CLOCK_CONFIG_FircSafeConfig().

enableMode [3/4]

uint32_t _scg_firc_config_t::enableMode

Enable mode, OR'ed value of _scg_firc_enable_mode.

Definition at line 575 of file fsl_clock.h.

enableMode [4/4]

uint8_t _scg_spll_config::enableMode

Enable mode, OR'ed value of _scg_spll_enable_mode

Definition at line 617 of file fsl_clock.h.

freq

uint32_t _scg_sosc_config::freq

System OSC frequency.

Definition at line 461 of file fsl_clock.h.

Referenced by ke1xf_clock_init().

g_xtal0Freq

volatile uint32_t g_xtal0Freq

extern

External XTAL0 (OSC0/SYSOSC) clock frequency.

The XTAL0/EXTAL0 (OSC0/SYSOSC) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, if XTAL0 is 8 MHz:

CLOCK_InitSysOsc(...); // Set up the OSC0/SYSOSC
CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value in the clock driver.

This is important for the multicore platforms where only one core needs to set up the OSC0/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtal0Freq to get a valid clock frequency.

Definition at line 75 of file fsl_clock.c.

Referenced by CLOCK_GetErClkFreq(), CLOCK_GetSysOscFreq(), and CLOCK_SetXtal0Freq().

g_xtal32Freq

volatile uint32_t g_xtal32Freq

extern

External XTAL32/EXTAL32 clock frequency.

The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.

This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.

Definition at line 77 of file fsl_clock.c.

Referenced by CLOCK_GetOsc32kClkFreq(), and CLOCK_SetXtal32Freq().

monitorMode [1/2]

scg_sosc_monitor_mode_t _scg_sosc_config::monitorMode

Clock monitor mode selected.

Definition at line 462 of file fsl_clock.h.

monitorMode [2/2]

scg_spll_monitor_mode_t _scg_spll_config::monitorMode

Clock monitor mode selected.

Definition at line 618 of file fsl_clock.h.

mult

uint8_t _scg_spll_config::mult

System PLL multiplier.

Definition at line 625 of file fsl_clock.h.

prediv

uint8_t _scg_spll_config::prediv

PLL reference clock divider.

Definition at line 624 of file fsl_clock.h.

range [1/2]

scg_sirc_range_t _scg_sirc_config::range

Slow IRC frequency range.

Definition at line 497 of file fsl_clock.h.

range [2/2]

scg_firc_range_t _scg_firc_config_t::range

Fast IRC frequency range.

Definition at line 580 of file fsl_clock.h.

src [1/2]

uint32_t _scg_sys_clk_config::src

System clock source, see scg_sys_clk_src_t.

Definition at line 388 of file fsl_clock.h.

Referenced by CLOCK_CONFIG_FircSafeConfig(), CLOCK_GetSysClkFreq(), and setClockConfig().

src [2/2]

scg_spll_src_t _scg_spll_config::src

Clock source.

Definition at line 623 of file fsl_clock.h.

trimCoar

uint8_t _scg_firc_trim_config::trimCoar

Trim coarse value; Irrelevant if trimMode is kSCG_FircTrimUpdate.

Definition at line 546 of file fsl_clock.h.

trimConfig

const scg_firc_trim_config_t* _scg_firc_config_t::trimConfig

Pointer to the FIRC trim configuration; set NULL to disable trim.

Definition at line 582 of file fsl_clock.h.

trimDiv

scg_firc_trim_div_t _scg_firc_trim_config::trimDiv

Trim predivided value for the system OSC.

Definition at line 544 of file fsl_clock.h.

trimFine

uint8_t _scg_firc_trim_config::trimFine

Trim fine value; Irrelevant if trimMode is kSCG_FircTrimUpdate.

Definition at line 547 of file fsl_clock.h.

trimMode

scg_firc_trim_mode_t _scg_firc_trim_config::trimMode

FIRC trim mode.

Definition at line 542 of file fsl_clock.h.

trimSrc

scg_firc_trim_src_t _scg_firc_trim_config::trimSrc

Trim source.

Definition at line 543 of file fsl_clock.h.

workMode

scg_sosc_mode_t _scg_sosc_config::workMode

OSC work mode.

Definition at line 468 of file fsl_clock.h.