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Functions | Variables
board.c File Reference

Detailed Description

Date
Oct 14, 2022
Author
Andrey Gusakov, 2022

Definition in file board.c.

Functions

static void gpio_init (stm32_gpio_t *gpiop, const gpio_setup_t *config)
 
static void stm32_gpio_init (void)
 
static void __early_sdram_wait_ready (void)
 
static void __early_sdram_delay (void)
 
static void __early_sdram_init (const SDRAMConfig *config)
 
static int __early_sdram_test (void *base, size_t size)
 
void __early_init (void)
 Early initialization code.
 
bool sdc_lld_is_card_inserted (SDCDriver *sdcp)
 SDC card detection.
 
bool sdc_lld_is_write_protected (SDCDriver *sdcp)
 SDC card write protection detection.
 
bool mmc_lld_is_card_inserted (MMCDriver *mmcp)
 MMC_SPI card detection.
 
bool mmc_lld_is_write_protected (MMCDriver *mmcp)
 MMC_SPI card write protection detection.
 

Variables

static const SDRAMConfig sdram_cfg
 
static const gpio_config_t gpio_default_config
 STM32 GPIO static initialization data.
 

Function Documentation

◆ __early_init()

void __early_init ( void  )

Early initialization code.

GPIO ports and system clocks are initialized before everything else.

Definition at line 357 of file board.c.

357 {
358
360 stm32_clock_init();
361
362 /*
363 * Initialise FSMC for SDRAM.
364 */
365#if 0
366 /* clear driver struct */
367 memset(&SDRAMD1, 0 sizeof(SDRAMD1));
368 sdramInit();
369 sdramStart(&SDRAMD1, &sdram_cfg);
370#else
372#endif
373
374 if (1) {
375 /* yes, hardcoded values */
376 __early_sdram_test((void *) 0xD0000000, 8 * 1024 * 1024);
377 }
378}
static void stm32_gpio_init(void)
Definition board.c:181
static void __early_sdram_init(const SDRAMConfig *config)
Definition board.c:260
static const SDRAMConfig sdram_cfg
Definition board.c:19
static int __early_sdram_test(void *base, size_t size)
Definition board.c:314
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◆ __early_sdram_delay()

static void __early_sdram_delay ( void  )
static

Definition at line 250 of file board.c.

251{
252 /* something > 100uS */
253 volatile int tmp = 168 * 1000 * 100;
254
255 do {
256 tmp--;
257 } while(tmp);
258}

Referenced by __early_sdram_init().

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◆ __early_sdram_init()

static void __early_sdram_init ( const SDRAMConfig *  config)
static

Definition at line 260 of file board.c.

261{
262 uint32_t command_target = 0;
263
264 #ifdef rccResetFSMC
265 rccResetFSMC();
266 #endif
267 rccEnableFSMC(FALSE);
268
269 SDRAM->SDCR1 = config->sdcr;
270 SDRAM->SDTR1 = config->sdtr;
271 SDRAM->SDCR2 = config->sdcr;
272 SDRAM->SDTR2 = config->sdtr;
273
274#if STM32_SDRAM_USE_SDRAM1
275 command_target |= FMC_SDCMR_CTB1;
276#endif
277#if STM32_SDRAM_USE_SDRAM2
278 command_target |= FMC_SDCMR_CTB2;
279#endif
280
281 /* Step 3: Configure a clock configuration enable command.*/
283 SDRAM->SDCMR = FMCCM_CLK_ENABLED | command_target;
284
285 /* Step 4: Insert delay (tipically 100uS).*/
287
288 /* Step 5: Configure a PALL (precharge all) command.*/
290 SDRAM->SDCMR = FMCCM_PALL | command_target;
291
292 /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
294 SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
295 (config->sdcmr & FMC_SDCMR_NRFS);
296
297 /* Step 6.2: Send the second command.*/
299 SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
300 (config->sdcmr & FMC_SDCMR_NRFS);
301
302 /* Step 7: Program the external memory mode register.*/
304 SDRAM->SDCMR = FMCCM_LOAD_MODE | command_target |
305 (config->sdcmr & FMC_SDCMR_MRD);
306
307 /* Step 8: Set clock.*/
309 SDRAM->SDRTR = config->sdrtr & FMC_SDRTR_COUNT;
310
312}
static constexpr persistent_config_s * config
static void __early_sdram_delay(void)
Definition board.c:250
static void __early_sdram_wait_ready(void)
Definition board.c:245

Referenced by __early_init().

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◆ __early_sdram_test()

static int __early_sdram_test ( void *  base,
size_t  size 
)
static

Definition at line 314 of file board.c.

315{
316 size_t i;
317 uint32_t *ptr = base;
318
319 /* test 0 */
320 for (i = 0; i < size / sizeof(uint32_t); i++) {
321 ptr[i] = 0;
322 }
323
324 for (i = 0; i < size / sizeof(uint32_t); i++) {
325 if (ptr[i] != 0)
326 return -1;
327 }
328
329 /* test 1 */
330 for (i = 0; i < size / sizeof(uint32_t); i++) {
331 ptr[i] = 0xffffffff;
332 }
333
334 for (i = 0; i < size / sizeof(uint32_t); i++) {
335 if (ptr[i] != 0xffffffff)
336 return -1;
337 }
338
339 /* test 2 */
340 for (i = 0; i < size / sizeof(uint32_t); i++) {
341 ptr[i] = i;
342 }
343
344 for (i = 0; i < size / sizeof(uint32_t); i++) {
345 if (ptr[i] != i)
346 return -1;
347 }
348
349 return 0;
350}
composite packet size

Referenced by __early_init().

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◆ __early_sdram_wait_ready()

static void __early_sdram_wait_ready ( void  )
static

Definition at line 245 of file board.c.

245 {
246 /* Wait until the SDRAM controller is ready */
247 while (SDRAM->SDSR & FMC_SDSR_BUSY);
248}

Referenced by __early_sdram_init().

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◆ gpio_init()

static void gpio_init ( stm32_gpio_t *  gpiop,
const gpio_setup_t *  config 
)
static

Definition at line 170 of file board.c.

170 {
171
172 gpiop->OTYPER = config->otyper;
173 gpiop->OSPEEDR = config->ospeedr;
174 gpiop->PUPDR = config->pupdr;
175 gpiop->ODR = config->odr;
176 gpiop->AFRL = config->afrl;
177 gpiop->AFRH = config->afrh;
178 gpiop->MODER = config->moder;
179}

Referenced by stm32_gpio_init().

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◆ mmc_lld_is_card_inserted()

bool mmc_lld_is_card_inserted ( MMCDriver *  mmcp)

MMC_SPI card detection.

Definition at line 406 of file board.c.

407{
408 UNUSED(mmcp);
409 /* TODO: Fill the implementation.*/
410 return true;
411}
UNUSED(samplingTimeSeconds)
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◆ mmc_lld_is_write_protected()

bool mmc_lld_is_write_protected ( MMCDriver *  mmcp)

MMC_SPI card write protection detection.

Definition at line 416 of file board.c.

417{
418 UNUSED(mmcp);
419 /* TODO: Fill the implementation.*/
420 return false;
421}
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◆ sdc_lld_is_card_inserted()

bool sdc_lld_is_card_inserted ( SDCDriver *  sdcp)

SDC card detection.

Definition at line 384 of file board.c.

385{
386 UNUSED(sdcp);
387 /* TODO: Fill the implementation.*/
388 return true;
389}
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◆ sdc_lld_is_write_protected()

bool sdc_lld_is_write_protected ( SDCDriver *  sdcp)

SDC card write protection detection.

Definition at line 394 of file board.c.

395{
396 UNUSED(sdcp);
397 /* TODO: Fill the implementation.*/
398 return false;
399}
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◆ stm32_gpio_init()

static void stm32_gpio_init ( void  )
static

Definition at line 181 of file board.c.

181 {
182
183 /* Enabling GPIO-related clocks, the mask comes from the
184 registry header file.*/
185 rccResetAHB1(STM32_GPIO_EN_MASK);
186 rccEnableAHB1(STM32_GPIO_EN_MASK, true);
187
188 /* Initializing all the defined GPIO ports.*/
189#if STM32_HAS_GPIOA
190 gpio_init(GPIOA, &gpio_default_config.PAData);
191#endif
192#if STM32_HAS_GPIOB
193 gpio_init(GPIOB, &gpio_default_config.PBData);
194#endif
195#if STM32_HAS_GPIOC
196 gpio_init(GPIOC, &gpio_default_config.PCData);
197#endif
198#if STM32_HAS_GPIOD
199 gpio_init(GPIOD, &gpio_default_config.PDData);
200#endif
201#if STM32_HAS_GPIOE
202 gpio_init(GPIOE, &gpio_default_config.PEData);
203#endif
204#if STM32_HAS_GPIOF
205 gpio_init(GPIOF, &gpio_default_config.PFData);
206#endif
207#if STM32_HAS_GPIOG
208 gpio_init(GPIOG, &gpio_default_config.PGData);
209#endif
210#if STM32_HAS_GPIOH
211 gpio_init(GPIOH, &gpio_default_config.PHData);
212#endif
213#if STM32_HAS_GPIOI
214 gpio_init(GPIOI, &gpio_default_config.PIData);
215#endif
216#if STM32_HAS_GPIOJ
217 gpio_init(GPIOJ, &gpio_default_config.PJData);
218#endif
219#if STM32_HAS_GPIOK
220 gpio_init(GPIOK, &gpio_default_config.PKData);
221#endif
222}
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config)
Definition board.c:170
static const gpio_config_t gpio_default_config
STM32 GPIO static initialization data.
Definition board.c:119

Referenced by __early_init().

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Variable Documentation

◆ gpio_default_config

const gpio_config_t gpio_default_config
static

STM32 GPIO static initialization data.

Definition at line 119 of file board.c.

119 {
120#if STM32_HAS_GPIOA
121 {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
122 VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
123#endif
124#if STM32_HAS_GPIOB
125 {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
126 VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
127#endif
128#if STM32_HAS_GPIOC
129 {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
130 VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
131#endif
132#if STM32_HAS_GPIOD
133 {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
134 VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
135#endif
136#if STM32_HAS_GPIOE
137 {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
138 VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
139#endif
140#if STM32_HAS_GPIOF
141 {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
142 VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
143#endif
144#if STM32_HAS_GPIOG
145 {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
146 VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
147#endif
148#if STM32_HAS_GPIOH
149 {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
150 VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
151#endif
152#if STM32_HAS_GPIOI
153 {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
154 VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
155#endif
156#if STM32_HAS_GPIOJ
157 {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
158 VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
159#endif
160#if STM32_HAS_GPIOK
161 {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
162 VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
163#endif
164};

Referenced by stm32_gpio_init().

◆ sdram_cfg

const SDRAMConfig sdram_cfg
static
Initial value:
= {
.sdcr = (uint32_t) (FMC_ColumnBits_Number_8b |
FMC_RowBits_Number_12b |
FMC_SDMemory_Width_16b |
FMC_InternalBank_Number_4 |
FMC_CAS_Latency_3 |
FMC_Write_Protection_Disable |
FMC_SDClock_Period_2 |
FMC_Read_Burst_Disable |
FMC_ReadPipe_Delay_1),
.sdtr = (uint32_t)( (2 - 1) |
(7 << 4) |
(4 << 8) |
(7 << 12) |
(2 << 16) |
(2 << 20) |
(2 << 24)),
.sdcmr = (uint32_t)(((4 - 1) << 5) |
((FMC_SDCMR_MRD_BURST_LENGTH_2 |
FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
FMC_SDCMR_MRD_CAS_LATENCY_3 |
FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
.sdrtr = (uint32_t)(683 << 1),
}

Definition at line 19 of file board.c.

19 {
20 .sdcr = (uint32_t) (FMC_ColumnBits_Number_8b |
21 FMC_RowBits_Number_12b |
22 FMC_SDMemory_Width_16b |
23 FMC_InternalBank_Number_4 |
24 FMC_CAS_Latency_3 |
25 FMC_Write_Protection_Disable |
26 FMC_SDClock_Period_2 |
27 FMC_Read_Burst_Disable |
28 FMC_ReadPipe_Delay_1),
29
30 .sdtr = (uint32_t)( (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
31 (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
32 (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
33 (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
34 (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
35 (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
36 (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
37
38 .sdcmr = (uint32_t)(((4 - 1) << 5) |
39 ((FMC_SDCMR_MRD_BURST_LENGTH_2 |
40 FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
41 FMC_SDCMR_MRD_CAS_LATENCY_3 |
42 FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
43 FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
44
45 /* if (STM32_SYSCLK == 180000000) ->
46 64ms / 4096 = 15.625us
47 15.625us * 90MHz = 1406 - 20 = 1386 */
48 //.sdrtr = (1386 << 1),
49 .sdrtr = (uint32_t)(683 << 1),
50};

Referenced by __early_init().

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