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board.c
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1/**
2 * @file boards/f429-208/board.c
3 *
4 * @date Oct 14, 2022
5 * @author Andrey Gusakov, 2022
6 */
7
8#include "hal.h"
9#include "hal_community.h"
10#include "hal_sdram_lld.h"
11/* for UNUSED() */
12#include "efilib.h"
13
14#include "board.h"
15
16/*
17 * SDRAM driver configuration structure.
18 */
19static const SDRAMConfig sdram_cfg = {
20 .sdcr = (uint32_t) (FMC_ColumnBits_Number_8b |
21 FMC_RowBits_Number_12b |
22 FMC_SDMemory_Width_16b |
23 FMC_InternalBank_Number_4 |
24 FMC_CAS_Latency_3 |
25 FMC_Write_Protection_Disable |
26 FMC_SDClock_Period_2 |
27 FMC_Read_Burst_Disable |
28 FMC_ReadPipe_Delay_1),
29
30 .sdtr = (uint32_t)( (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
31 (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
32 (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
33 (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
34 (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
35 (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
36 (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
37
38 .sdcmr = (uint32_t)(((4 - 1) << 5) |
39 ((FMC_SDCMR_MRD_BURST_LENGTH_2 |
40 FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
41 FMC_SDCMR_MRD_CAS_LATENCY_3 |
42 FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
43 FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
44
45 /* if (STM32_SYSCLK == 180000000) ->
46 64ms / 4096 = 15.625us
47 15.625us * 90MHz = 1406 - 20 = 1386 */
48 //.sdrtr = (1386 << 1),
49 .sdrtr = (uint32_t)(683 << 1),
50};
51
52/*===========================================================================*/
53/* Driver local definitions. */
54/*===========================================================================*/
55
56/*===========================================================================*/
57/* Driver exported variables. */
58/*===========================================================================*/
59
60/*===========================================================================*/
61/* Driver local variables and types. */
62/*===========================================================================*/
63
64/**
65 * @brief Type of STM32 GPIO port setup.
66 */
67typedef struct {
68 uint32_t moder;
69 uint32_t otyper;
70 uint32_t ospeedr;
71 uint32_t pupdr;
72 uint32_t odr;
73 uint32_t afrl;
74 uint32_t afrh;
75} gpio_setup_t;
76
77/**
78 * @brief Type of STM32 GPIO initialization data.
79 */
80typedef struct {
81#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
82 gpio_setup_t PAData;
83#endif
84#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
85 gpio_setup_t PBData;
86#endif
87#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
88 gpio_setup_t PCData;
89#endif
90#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
91 gpio_setup_t PDData;
92#endif
93#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
94 gpio_setup_t PEData;
95#endif
96#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
97 gpio_setup_t PFData;
98#endif
99#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
100 gpio_setup_t PGData;
101#endif
102#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
103 gpio_setup_t PHData;
104#endif
105#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
106 gpio_setup_t PIData;
107#endif
108#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
109 gpio_setup_t PJData;
110#endif
111#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
112 gpio_setup_t PKData;
113#endif
114} gpio_config_t;
115
116/**
117 * @brief STM32 GPIO static initialization data.
118 */
119static const gpio_config_t gpio_default_config = {
120#if STM32_HAS_GPIOA
121 {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
122 VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
123#endif
124#if STM32_HAS_GPIOB
125 {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
126 VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
127#endif
128#if STM32_HAS_GPIOC
129 {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
130 VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
131#endif
132#if STM32_HAS_GPIOD
133 {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
134 VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
135#endif
136#if STM32_HAS_GPIOE
137 {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
138 VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
139#endif
140#if STM32_HAS_GPIOF
141 {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
142 VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
143#endif
144#if STM32_HAS_GPIOG
145 {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
146 VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
147#endif
148#if STM32_HAS_GPIOH
149 {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
150 VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
151#endif
152#if STM32_HAS_GPIOI
153 {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
154 VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
155#endif
156#if STM32_HAS_GPIOJ
157 {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
158 VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
159#endif
160#if STM32_HAS_GPIOK
161 {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
162 VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
163#endif
164};
165
166/*===========================================================================*/
167/* Driver local functions. */
168/*===========================================================================*/
169
170static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
171
172 gpiop->OTYPER = config->otyper;
173 gpiop->OSPEEDR = config->ospeedr;
174 gpiop->PUPDR = config->pupdr;
175 gpiop->ODR = config->odr;
176 gpiop->AFRL = config->afrl;
177 gpiop->AFRH = config->afrh;
178 gpiop->MODER = config->moder;
179}
180
181static void stm32_gpio_init(void) {
182
183 /* Enabling GPIO-related clocks, the mask comes from the
184 registry header file.*/
185 rccResetAHB1(STM32_GPIO_EN_MASK);
186 rccEnableAHB1(STM32_GPIO_EN_MASK, true);
187
188 /* Initializing all the defined GPIO ports.*/
189#if STM32_HAS_GPIOA
190 gpio_init(GPIOA, &gpio_default_config.PAData);
191#endif
192#if STM32_HAS_GPIOB
193 gpio_init(GPIOB, &gpio_default_config.PBData);
194#endif
195#if STM32_HAS_GPIOC
196 gpio_init(GPIOC, &gpio_default_config.PCData);
197#endif
198#if STM32_HAS_GPIOD
199 gpio_init(GPIOD, &gpio_default_config.PDData);
200#endif
201#if STM32_HAS_GPIOE
202 gpio_init(GPIOE, &gpio_default_config.PEData);
203#endif
204#if STM32_HAS_GPIOF
205 gpio_init(GPIOF, &gpio_default_config.PFData);
206#endif
207#if STM32_HAS_GPIOG
208 gpio_init(GPIOG, &gpio_default_config.PGData);
209#endif
210#if STM32_HAS_GPIOH
211 gpio_init(GPIOH, &gpio_default_config.PHData);
212#endif
213#if STM32_HAS_GPIOI
214 gpio_init(GPIOI, &gpio_default_config.PIData);
215#endif
216#if STM32_HAS_GPIOJ
217 gpio_init(GPIOJ, &gpio_default_config.PJData);
218#endif
219#if STM32_HAS_GPIOK
220 gpio_init(GPIOK, &gpio_default_config.PKData);
221#endif
222}
223
224/*===========================================================================*/
225/* Driver interrupt handlers. */
226/*===========================================================================*/
227
228/*===========================================================================*/
229/* Driver exported functions. */
230/*===========================================================================*/
231
232#define SDRAM ((FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE)
233
234/**
235 * FMC_Command_Mode
236 */
237#define FMCCM_NORMAL ((uint32_t)0x00000000)
238#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001)
239#define FMCCM_PALL ((uint32_t)0x00000002)
240#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003)
241#define FMCCM_LOAD_MODE ((uint32_t)0x00000004)
242#define FMCCM_SELFREFRESH ((uint32_t)0x00000005)
243#define FMCCM_POWER_DOWN ((uint32_t)0x00000006)
244
245static void __early_sdram_wait_ready(void) {
246 /* Wait until the SDRAM controller is ready */
247 while (SDRAM->SDSR & FMC_SDSR_BUSY);
248}
249
250static void __early_sdram_delay(void)
251{
252 /* something > 100uS */
253 volatile int tmp = 168 * 1000 * 100;
254
255 do {
256 tmp--;
257 } while(tmp);
258}
259
260static void __early_sdram_init(const SDRAMConfig *config)
261{
262 uint32_t command_target = 0;
263
264 #ifdef rccResetFSMC
265 rccResetFSMC();
266 #endif
267 rccEnableFSMC(FALSE);
268
269 SDRAM->SDCR1 = config->sdcr;
270 SDRAM->SDTR1 = config->sdtr;
271 SDRAM->SDCR2 = config->sdcr;
272 SDRAM->SDTR2 = config->sdtr;
273
274#if STM32_SDRAM_USE_SDRAM1
275 command_target |= FMC_SDCMR_CTB1;
276#endif
277#if STM32_SDRAM_USE_SDRAM2
278 command_target |= FMC_SDCMR_CTB2;
279#endif
280
281 /* Step 3: Configure a clock configuration enable command.*/
282 __early_sdram_wait_ready();
283 SDRAM->SDCMR = FMCCM_CLK_ENABLED | command_target;
284
285 /* Step 4: Insert delay (tipically 100uS).*/
286 __early_sdram_delay();
287
288 /* Step 5: Configure a PALL (precharge all) command.*/
289 __early_sdram_wait_ready();
290 SDRAM->SDCMR = FMCCM_PALL | command_target;
291
292 /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
293 __early_sdram_wait_ready();
294 SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
295 (config->sdcmr & FMC_SDCMR_NRFS);
296
297 /* Step 6.2: Send the second command.*/
298 __early_sdram_wait_ready();
299 SDRAM->SDCMR = FMCCM_AUTO_REFRESH | command_target |
300 (config->sdcmr & FMC_SDCMR_NRFS);
301
302 /* Step 7: Program the external memory mode register.*/
303 __early_sdram_wait_ready();
304 SDRAM->SDCMR = FMCCM_LOAD_MODE | command_target |
305 (config->sdcmr & FMC_SDCMR_MRD);
306
307 /* Step 8: Set clock.*/
308 __early_sdram_wait_ready();
309 SDRAM->SDRTR = config->sdrtr & FMC_SDRTR_COUNT;
310
311 __early_sdram_wait_ready();
312}
313
314static int __early_sdram_test(void *base, size_t size)
315{
316 size_t i;
317 uint32_t *ptr = base;
318
319 /* test 0 */
320 for (i = 0; i < size / sizeof(uint32_t); i++) {
321 ptr[i] = 0;
322 }
323
324 for (i = 0; i < size / sizeof(uint32_t); i++) {
325 if (ptr[i] != 0)
326 return -1;
327 }
328
329 /* test 1 */
330 for (i = 0; i < size / sizeof(uint32_t); i++) {
331 ptr[i] = 0xffffffff;
332 }
333
334 for (i = 0; i < size / sizeof(uint32_t); i++) {
335 if (ptr[i] != 0xffffffff)
336 return -1;
337 }
338
339 /* test 2 */
340 for (i = 0; i < size / sizeof(uint32_t); i++) {
341 ptr[i] = i;
342 }
343
344 for (i = 0; i < size / sizeof(uint32_t); i++) {
345 if (ptr[i] != i)
346 return -1;
347 }
348
349 return 0;
350}
351
352/**
353 * @brief Early initialization code.
354 * @details GPIO ports and system clocks are initialized before everything
355 * else.
356 */
357void __early_init(void) {
358
359 stm32_gpio_init();
360 stm32_clock_init();
361
362 /*
363 * Initialise FSMC for SDRAM.
364 */
365#if 0
366 /* clear driver struct */
367 memset(&SDRAMD1, 0 sizeof(SDRAMD1));
368 sdramInit();
369 sdramStart(&SDRAMD1, &sdram_cfg);
370#else
371 __early_sdram_init(&sdram_cfg);
372#endif
373
374 if (1) {
375 /* yes, hardcoded values */
376 __early_sdram_test((void *) 0xD0000000, 8 * 1024 * 1024);
377 }
378}
379
380#if HAL_USE_SDC || defined(__DOXYGEN__)
381/**
382 * @brief SDC card detection.
383 */
384bool sdc_lld_is_card_inserted(SDCDriver *sdcp)
385{
386 UNUSED(sdcp);
387 /* TODO: Fill the implementation.*/
388 return true;
389}
390
391/**
392 * @brief SDC card write protection detection.
393 */
394bool sdc_lld_is_write_protected(SDCDriver *sdcp)
395{
396 UNUSED(sdcp);
397 /* TODO: Fill the implementation.*/
398 return false;
399}
400#endif /* HAL_USE_SDC */
401
402#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
403/**
404 * @brief MMC_SPI card detection.
405 */
406bool mmc_lld_is_card_inserted(MMCDriver *mmcp)
407{
408 UNUSED(mmcp);
409 /* TODO: Fill the implementation.*/
410 return true;
411}
412
413/**
414 * @brief MMC_SPI card write protection detection.
415 */
416bool mmc_lld_is_write_protected(MMCDriver *mmcp)
417{
418 UNUSED(mmcp);
419 /* TODO: Fill the implementation.*/
420 return false;
421}
422#endif
__early_init
void __early_init(void)
Definition board.c:21
config
static constexpr persistent_config_s * config
Definition engine_configuration.h:81
sdc_lld_is_write_protected
bool sdc_lld_is_write_protected(SDCDriver *sdcp)
SDC card write protection detection.
Definition board.c:394
mmc_lld_is_card_inserted
bool mmc_lld_is_card_inserted(MMCDriver *mmcp)
MMC_SPI card detection.
Definition board.c:406
mmc_lld_is_write_protected
bool mmc_lld_is_write_protected(MMCDriver *mmcp)
MMC_SPI card write protection detection.
Definition board.c:416
stm32_gpio_init
static void stm32_gpio_init(void)
Definition board.c:181
gpio_init
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config)
Definition board.c:170
gpio_default_config
static const gpio_config_t gpio_default_config
STM32 GPIO static initialization data.
Definition board.c:119
__early_sdram_delay
static void __early_sdram_delay(void)
Definition board.c:250
__early_sdram_init
static void __early_sdram_init(const SDRAMConfig *config)
Definition board.c:260
sdram_cfg
static const SDRAMConfig sdram_cfg
Definition board.c:19
__early_sdram_wait_ready
static void __early_sdram_wait_ready(void)
Definition board.c:245
__early_sdram_test
static int __early_sdram_test(void *base, size_t size)
Definition board.c:314
sdc_lld_is_card_inserted
bool sdc_lld_is_card_inserted(SDCDriver *sdcp)
SDC card detection.
Definition board.c:384
UNUSED
UNUSED(samplingTimeSeconds)
size
composite packet size
Definition tooth_logger.cpp:23
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