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stm32h7xx_hal_flash_ex.h
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1/**
2 ******************************************************************************
3 * @file stm32H7xx_hal_flash_ex.h
4 * @author MCD Application Team
5 * @brief Header file of FLASH HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef STM32H7xx_HAL_FLASH_EX_H
22#define STM32H7xx_HAL_FLASH_EX_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32h7xx_hal_def.h"
30
31/** @addtogroup STM32H7xx_HAL_Driver
32 * @{
33 */
34
35/** @addtogroup FLASHEx
36 * @{
37 */
38
39/* Exported types ------------------------------------------------------------*/
40/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
41 * @{
42 */
43
44/**
45 * @brief FLASH Erase structure definition
46 */
47typedef struct
48{
49 uint32_t TypeErase; /*!< Mass erase or sector Erase.
50 This parameter can be a value of @ref FLASHEx_Type_Erase */
51
52 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
53 This parameter must be a value of @ref FLASHEx_Banks */
54
55 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
56 This parameter must be a value of @ref FLASH_Sectors */
57
58 uint32_t NbSectors; /*!< Number of sectors to be erased.
59 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
60
61 uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
62 This parameter must be a value of @ref FLASHEx_Voltage_Range */
63
64} FLASH_EraseInitTypeDef;
65
66
67/**
68 * @brief FLASH Option Bytes Program structure definition
69 */
70typedef struct
71{
72 uint32_t OptionType; /*!< Option byte to be configured.
73 This parameter can be a value of @ref FLASHEx_Option_Type */
74
75 uint32_t WRPState; /*!< Write protection activation or deactivation.
76 This parameter can be a value of @ref FLASHEx_WRP_State */
77
78 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
79 The value of this parameter depend on device used within the same series */
80
81 uint32_t RDPLevel; /*!< Set the read protection level.
82 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
83
84 uint32_t BORLevel; /*!< Set the BOR Level.
85 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
86
87 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
88 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
89
90 uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
91 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
92
93 uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .
94 This parameter must be a value of @ref FLASHEx_Banks */
95
96 uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not
97 when RDP level decreased from Level 1 to Level 0 or during a mass erase.
98 This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
99
100 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
101 This parameter must be a value between begin and end of a bank */
102
103 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
104 This parameter must be a value between PCROP Start address and end of a bank */
105
106 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
107 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
108
109 uint32_t BootAddr0; /*!< Boot Address 0.
110 This parameter must be a value between begin and end of a bank */
111
112 uint32_t BootAddr1; /*!< Boot Address 1.
113 This parameter must be a value between begin and end of a bank */
114#if defined(DUAL_CORE)
115 uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
116 or both.
117 This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
118
119 uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0.
120 This parameter must be a value between begin and end of a bank */
121
122 uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1.
123 This parameter must be a value between begin and end of a bank */
124#endif /*DUAL_CORE*/
125
126 uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
127 when RDP level decreased from Level 1 to Level 0 or during a mass erase.
128 This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
129
130 uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
131 This parameter must be a value between begin address and end address of bank1 */
132
133 uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address.
134 This parameter must be a value between Secure Area Start address and end address of a bank1 */
135
136#if defined (FLASH_OTPBL_LOCKBL)
137 uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked.
138 This parameter must be a value of @ref FLASHEx_OTP_Blocks */
139#endif /* FLASH_OTPBL_LOCKBL */
140
141#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
142 uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM.
143 This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */
144#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
145
146#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
147 uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost.
148 This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */
149#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
150
151} FLASH_OBProgramInitTypeDef;
152
153/**
154 * @brief FLASH Erase structure definition
155 */
156typedef struct
157{
158 uint32_t TypeCRC; /*!< CRC Selection Type.
159 This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
160
161 uint32_t BurstSize; /*!< CRC Burst Size.
162 This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
163
164 uint32_t Bank; /*!< Select bank where CRC computation is enabled.
165 This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
166
167 uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation
168 This parameter must be a value of @ref FLASH_Sectors */
169
170 uint32_t NbSectors; /*!< Number of sectors to be computed.
171 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
172
173 uint32_t CRCStartAddr; /*!< CRC Start address.
174 This parameter must be a value between begin address and end address of a bank */
175
176 uint32_t CRCEndAddr; /*!< CRC End address.
177 This parameter must be a value between CRC Start address and end address of a bank */
178
179} FLASH_CRCInitTypeDef;
180
181/**
182 * @}
183 */
184/* Exported constants --------------------------------------------------------*/
185
186/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
187 * @{
188 */
189
190/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
191 * @{
192 */
193#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */
194#define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */
195/**
196 * @}
197 */
198
199#if defined (FLASH_CR_PSIZE)
200/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
201 * @{
202 */
203#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */
204#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */
205#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */
206#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */
207/**
208 * @}
209 */
210#endif /* FLASH_CR_PSIZE */
211
212/** @defgroup FLASHEx_WRP_State FLASH WRP State
213 * @{
214 */
215#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
216#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */
217/**
218 * @}
219 */
220
221/** @defgroup FLASHEx_Option_Type FLASH Option Type
222 * @{
223 */
224#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
225#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
226#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
227#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
228#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */
229#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */
230#if defined (DUAL_CORE)
231#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */
232#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */
233#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */
234#else /* Single core */
235#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */
236#endif /*DUAL_CORE*/
237#if defined (FLASH_OTPBL_LOCKBL)
238#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */
239#endif /* FLASH_OTPBL_LOCKBL */
240#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
241#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */
242#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
243#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
244#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */
245#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
246
247#if defined (DUAL_CORE)
248#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
249 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
250 OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */
251#elif defined (FLASH_OTPBL_LOCKBL)
252#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
253 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
254 OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */
255#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
256#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
257 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
258 OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */
259#else
260#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
261 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
262 OPTIONBYTE_BOOTADD) /*!< All option byte configuration */
263#endif /* DUAL_CORE */
264/**
265 * @}
266 */
267
268/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
269 * @{
270 */
271#define OB_RDP_LEVEL_0 0xAA00U
272#define OB_RDP_LEVEL_1 0x5500U
273#define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2
274 it s no more possible to go back to level 1 or 0 */
275/**
276 * @}
277 */
278
279/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
280 * @{
281 */
282#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */
283#define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */
284/**
285 * @}
286 */
287
288
289/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
290 * @{
291 */
292#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */
293#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */
294/**
295 * @}
296 */
297
298/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
299 * @{
300 */
301#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */
302#define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */
303/**
304 * @}
305 */
306
307/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
308 * @{
309 */
310#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */
311#define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */
312/**
313 * @}
314 */
315
316/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
317 * @{
318 */
319#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */
320#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
321/**
322 * @}
323 */
324
325/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
326 * @{
327 */
328#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
329#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */
330/**
331 * @}
332 */
333
334/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
335 * @{
336 */
337#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */
338#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */
339#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */
340#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */
341
342#define OB_BOR_OFF OB_BOR_LEVEL0
343/**
344 * @}
345 */
346
347
348
349/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
350 * @{
351 */
352#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */
353#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */
354#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */
355#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */
356#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */
357#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */
358#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */
359/**
360 * @}
361 */
362
363/** @defgroup FLASH_Latency FLASH Latency
364 * @{
365 */
366#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
367#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
368#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
369#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
370#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
371#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
372#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
373#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
374#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */
375#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */
376#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
377#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
378#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
379#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
380#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
381#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
382/**
383 * @}
384 */
385
386/** @defgroup FLASHEx_Banks FLASH Banks
387 * @{
388 */
389#define FLASH_BANK_1 0x01U /*!< Bank 1 */
390#if defined (DUAL_BANK)
391#define FLASH_BANK_2 0x02U /*!< Bank 2 */
392#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
393#endif /* DUAL_BANK */
394/**
395 * @}
396 */
397
398/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
399 * @{
400 */
401#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
402 is decreased from Level 1 to Level 0 or during a mass erase */
403#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
404 decreased from Level 1 to Level 0 (full mass erase) */
405
406/**
407 * @}
408 */
409
410/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
411 * @{
412 */
413#if (FLASH_SECTOR_TOTAL == 128)
414#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */
415#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */
416#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */
417#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */
418#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */
419#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */
420#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */
421#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */
422#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */
423#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */
424#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */
425#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */
426#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */
427#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */
428#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */
429#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */
430#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */
431#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */
432#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */
433#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */
434#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */
435#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */
436#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */
437#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */
438#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */
439#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */
440#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */
441#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */
442#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */
443#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */
444#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */
445#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */
446#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */
447#else
448#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
449#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
450#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
451#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
452#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
453#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
454#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
455#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
456#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */
457#endif /* FLASH_SECTOR_TOTAL == 128 */
458/**
459 * @}
460 */
461
462/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY
463 * @{
464 */
465#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */
466#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */
467/**
468 * @}
469 */
470
471/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE
472 * @{
473 */
474#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */
475#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
476#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
477#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */
478/**
479 * @}
480 */
481
482#if defined(DUAL_CORE)
483/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7
484 * @{
485 */
486#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */
487#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */
488
489/**
490 * @}
491 */
492
493/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4
494 * @{
495 */
496#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */
497#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */
498/**
499 * @}
500 */
501#endif /* DUAL_CORE */
502
503/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
504 * @{
505 */
506#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */
507#define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */
508/**
509 * @}
510 */
511
512#if defined(DUAL_CORE)
513/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW
514 * @{
515 */
516#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/
517#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/
518/**
519 * @}
520 */
521#endif
522
523/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1
524 * @{
525 */
526#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */
527#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */
528/**
529 * @}
530 */
531
532/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1
533 * @{
534 */
535#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */
536#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */
537/**
538 * @}
539 */
540
541#if defined (FLASH_OPTSR_NRST_STOP_D2)
542/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
543 * @{
544 */
545#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */
546#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
547/**
548 * @}
549 */
550
551/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2
552 * @{
553 */
554#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */
555#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
556/**
557 * @}
558 */
559#endif /* FLASH_OPTSR_NRST_STOP_D2 */
560
561/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
562 * @{
563 */
564#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */
565#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */
566/**
567 * @}
568 */
569
570/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
571 * @{
572 */
573#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */
574#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
575/**
576 * @}
577 */
578
579#if defined (FLASH_OPTSR_VDDMMC_HSLV)
580/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
581 * @{
582 */
583#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */
584#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
585/**
586 * @}
587 */
588#endif /* FLASH_OPTSR_VDDMMC_HSLV */
589
590#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
591/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST
592 * @{
593 */
594#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */
595#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */
596/**
597 * @}
598 */
599#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
600
601#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
602/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED
603 * @{
604 */
605#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */
606#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */
607#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */
608#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */
609/**
610 * @}
611 */
612#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
613
614 /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
615 * @{
616 */
617#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */
618#define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/
619#define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/
620#define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */
621#define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */
622#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */
623#define OB_USER_SECURITY 0x0040U /*!< security selection */
624#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */
625#if defined (DUAL_BANK)
626#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */
627#endif /* DUAL_BANK */
628#if defined (FLASH_OPTSR_VDDMMC_HSLV)
629#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */
630#endif /* FLASH_OPTSR_VDDMMC_HSLV */
631#if defined (DUAL_CORE)
632#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */
633#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */
634#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */
635#endif /*DUAL_CORE*/
636#if defined (FLASH_OPTSR_NRST_STOP_D2)
637#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */
638#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */
639#endif /* FLASH_OPTSR_NRST_STOP_D2 */
640
641#if defined (DUAL_CORE)
642#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
643 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
644 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
645 OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
646 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
647#elif defined (FLASH_OPTSR_VDDMMC_HSLV)
648#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
649 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
650 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
651 OB_USER_VDDMMC_HSLV)
652#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
653#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
654 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
655 OB_USER_SECURITY | OB_USER_IOHSLV |\
656 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
657#else
658#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
659 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
660 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
661#endif /* DUAL_CORE */
662/**
663 * @}
664 */
665
666/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
667 * @{
668 */
669#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */
670#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */
671#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */
672/**
673 * @}
674 */
675
676/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP
677 * @{
678 */
679#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level
680 is decreased from Level 1 to Level 0 or during a mass erase */
681#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
682 decreased from Level 1 to Level 0 (full mass erase) */
683/**
684 * @}
685 */
686
687/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type
688 * @{
689 */
690#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */
691#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */
692#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */
693/**
694 * @}
695 */
696
697/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size
698 * @{
699 */
700#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */
701#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */
702#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */
703#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */
704/**
705 * @}
706 */
707
708/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay
709 * @{
710 */
711#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */
712#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */
713#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */
714#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */
715/**
716 * @}
717 */
718
719#if defined (FLASH_OTPBL_LOCKBL)
720/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
721 * @{
722 */
723#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */
724#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */
725#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */
726#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */
727#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */
728#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */
729#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */
730#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */
731#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */
732#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */
733#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */
734#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */
735#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */
736#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */
737#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */
738#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */
739#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */
740/**
741 * @}
742 */
743#endif /* FLASH_OTPBL_LOCKBL */
744
745/* Exported macro ------------------------------------------------------------*/
746/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
747 * @{
748 */
749/**
750 * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
751 * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
752 * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
753 * @retval The FLASH Boot Base Adress
754 */
755#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
756 /**
757 * @}
758 */
759
760#if defined (FLASH_CR_PSIZE)
761/**
762 * @brief Set the FLASH Program/Erase parallelism.
763 * @param __PSIZE__ FLASH Program/Erase parallelism
764 * This parameter can be a value of @ref FLASH_Program_Parallelism
765 * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
766 * @retval none
767 */
768#if defined (DUAL_BANK)
769#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
770 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
771 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
772#else
773#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
774#endif /* DUAL_BANK */
775
776/**
777 * @brief Get the FLASH Program/Erase parallelism.
778 * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)
779 * @retval FLASH Program/Erase parallelism
780 * This return value can be a value of @ref FLASH_Program_Parallelism
781 */
782#if defined (DUAL_BANK)
783#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
784 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
785 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
786#else
787#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
788#endif /* DUAL_BANK */
789
790#endif /* FLASH_CR_PSIZE */
791
792/**
793 * @brief Set the FLASH Programming Delay.
794 * @param __DELAY__ FLASH Programming Delay
795 * This parameter can be a value of @ref FLASHEx_Programming_Delay
796 * @retval none
797 */
798#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
799
800/**
801 * @brief Get the FLASH Programming Delay.
802 * @retval FLASH Programming Delay
803 * This return value can be a value of @ref FLASHEx_Programming_Delay
804 */
805#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
806
807/* Exported functions --------------------------------------------------------*/
808/** @addtogroup FLASHEx_Exported_Functions
809 * @{
810 */
811
812/** @addtogroup FLASHEx_Exported_Functions_Group1
813 * @{
814 */
815/* Extension Program operation functions *************************************/
816HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
817HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
818HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
819void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
820
821HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
822HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
823#if defined (DUAL_BANK)
824HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
825HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
826#endif /* DUAL_BANK */
827
828HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
829
830/**
831 * @}
832 */
833
834/**
835 * @}
836 */
837/* Private types -------------------------------------------------------------*/
838/* Private variables ---------------------------------------------------------*/
839/* Private constants ---------------------------------------------------------*/
840/* Private macros ------------------------------------------------------------*/
841/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
842 * @{
843 */
844
845/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
846 * @{
847 */
848
849#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
850 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
851
852#if defined (FLASH_CR_PSIZE)
853#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
854 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
855 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
856 ((RANGE) == FLASH_VOLTAGE_RANGE_4))
857#endif /* FLASH_CR_PSIZE */
858
859#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
860 ((VALUE) == OB_WRPSTATE_ENABLE))
861
862#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
863 (((VALUE) & ~OPTIONBYTE_ALL) == 0U))
864
865#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
866
867#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
868 ((LEVEL) == OB_RDP_LEVEL_1) ||\
869 ((LEVEL) == OB_RDP_LEVEL_2))
870
871#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
872
873#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
874
875#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
876
877#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
878
879#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
880
881#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
882
883#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
884 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
885
886#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
887 ((LATENCY) == FLASH_LATENCY_1) || \
888 ((LATENCY) == FLASH_LATENCY_2) || \
889 ((LATENCY) == FLASH_LATENCY_3) || \
890 ((LATENCY) == FLASH_LATENCY_4) || \
891 ((LATENCY) == FLASH_LATENCY_5) || \
892 ((LATENCY) == FLASH_LATENCY_6) || \
893 ((LATENCY) == FLASH_LATENCY_7) || \
894 ((LATENCY) == FLASH_LATENCY_8) || \
895 ((LATENCY) == FLASH_LATENCY_9) || \
896 ((LATENCY) == FLASH_LATENCY_10) || \
897 ((LATENCY) == FLASH_LATENCY_11) || \
898 ((LATENCY) == FLASH_LATENCY_12) || \
899 ((LATENCY) == FLASH_LATENCY_13) || \
900 ((LATENCY) == FLASH_LATENCY_14) || \
901 ((LATENCY) == FLASH_LATENCY_15))
902
903#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
904
905#if (FLASH_SECTOR_TOTAL == 8U)
906#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
907#else
908#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
909#endif /* FLASH_SECTOR_TOTAL == 8U */
910
911#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
912 ((CONFIG) == OB_PCROP_RDP_ERASE))
913
914#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
915 ((CONFIG) == OB_SECURE_RDP_ERASE))
916
917#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
918
919#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
920
921#if defined (FLASH_OPTSR_VDDMMC_HSLV)
922#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
923#endif /* FLASH_OPTSR_VDDMMC_HSLV */
924
925#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
926#if defined (DUAL_CORE)
927#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
928#endif /* DUAL_CORE */
929#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
930
931#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
932
933#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
934
935#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
936
937#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
938 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
939
940#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
941
942#if defined (DUAL_CORE)
943#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
944
945#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
946#endif /* DUAL_CORE */
947
948#if defined (FLASH_OPTSR_NRST_STOP_D2)
949#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
950
951#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
952#endif /* FLASH_OPTSR_NRST_STOP_D2 */
953
954#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
955#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
956 ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
957#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
958
959#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
960#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
961#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
962
963#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
964 (((TYPE) & ~OB_USER_ALL) == 0U))
965
966#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
967 ((VALUE) == OB_BOOT_ADD1) || \
968 ((VALUE) == OB_BOOT_ADD_BOTH))
969
970#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
971 ((VALUE) == FLASH_CRC_SECTORS) || \
972 ((VALUE) == FLASH_CRC_BANK))
973
974#if defined (FLASH_OTPBL_LOCKBL)
975#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
976#endif /* FLASH_OTPBL_LOCKBL */
977/**
978 * @}
979 */
980
981/**
982 * @}
983 */
984
985/* Private functions ---------------------------------------------------------*/
986/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
987 * @{
988 */
989void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
990/**
991 * @}
992 */
993
994/**
995 * @}
996 */
997
998/**
999 * @}
1000 */
1001
1002/**
1003 * @}
1004 */
1005
1006#ifdef __cplusplus
1007}
1008#endif
1009
1010#endif /* STM32H7xx_HAL_FLASH_EX_H */
1011
1012/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_FLASHEx_OBProgram
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
Definition stm32f4xx_hal_flash_ex.c:314
HAL_FLASHEx_Lock_Bank2
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
Locks the FLASH Bank2 control registers access.
Definition stm32h7xx_hal_flash_ex.c:689
HAL_FLASHEx_Unlock_Bank2
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
Unlock the FLASH Bank2 control registers access.
Definition stm32h7xx_hal_flash_ex.c:667
HAL_FLASHEx_Erase
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
Perform a mass erase or erase the specified FLASH memory sectors.
Definition stm32f4xx_hal_flash_ex.c:190
HAL_FLASHEx_OBGetConfig
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
Definition stm32f4xx_hal_flash_ex.c:402
HAL_FLASHEx_ComputeCRC
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
Definition stm32h7xx_hal_flash_ex.c:708
HAL_FLASHEx_Unlock_Bank1
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
Unlock the FLASH Bank1 control registers access.
Definition stm32h7xx_hal_flash_ex.c:633
HAL_FLASHEx_Lock_Bank1
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
Locks the FLASH Bank1 control registers access.
Definition stm32h7xx_hal_flash_ex.c:655
HAL_FLASHEx_Erase_IT
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled.
Definition stm32f4xx_hal_flash_ex.c:261
FLASH_Erase_Sector
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
Erase the specified FLASH memory sector.
Definition stm32f4xx_hal_flash_ex.c:637
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
FLASH_CRCInitTypeDef
FLASH Erase structure definition.
Definition stm32h7xx_hal_flash_ex.h:157
FLASH_CRCInitTypeDef::TypeCRC
uint32_t TypeCRC
Definition stm32h7xx_hal_flash_ex.h:158
FLASH_CRCInitTypeDef::BurstSize
uint32_t BurstSize
Definition stm32h7xx_hal_flash_ex.h:161
FLASH_CRCInitTypeDef::CRCStartAddr
uint32_t CRCStartAddr
Definition stm32h7xx_hal_flash_ex.h:173
FLASH_CRCInitTypeDef::Sector
uint32_t Sector
Definition stm32h7xx_hal_flash_ex.h:167
FLASH_CRCInitTypeDef::NbSectors
uint32_t NbSectors
Definition stm32h7xx_hal_flash_ex.h:170
FLASH_CRCInitTypeDef::Bank
uint32_t Bank
Definition stm32h7xx_hal_flash_ex.h:164
FLASH_CRCInitTypeDef::CRCEndAddr
uint32_t CRCEndAddr
Definition stm32h7xx_hal_flash_ex.h:176
FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition.
Definition stm32f4xx_hal_flash_ex.h:88
FLASH_OBProgramInitTypeDef::CM4BootConfig
uint32_t CM4BootConfig
Definition stm32h7xx_hal_flash_ex.h:115
FLASH_OBProgramInitTypeDef::PCROPConfig
uint32_t PCROPConfig
Definition stm32h7xx_hal_flash_ex.h:96
FLASH_OBProgramInitTypeDef::OTPBlockLock
uint32_t OTPBlockLock
Definition stm32h7xx_hal_flash_ex.h:137
FLASH_OBProgramInitTypeDef::SecureAreaConfig
uint32_t SecureAreaConfig
Definition stm32h7xx_hal_flash_ex.h:126
FLASH_OBProgramInitTypeDef::SharedRamConfig
uint32_t SharedRamConfig
Definition stm32h7xx_hal_flash_ex.h:142
FLASH_OBProgramInitTypeDef::SecureAreaStartAddr
uint32_t SecureAreaStartAddr
Definition stm32h7xx_hal_flash_ex.h:130
FLASH_OBProgramInitTypeDef::FreqBoostState
uint32_t FreqBoostState
Definition stm32h7xx_hal_flash_ex.h:147
FLASH_OBProgramInitTypeDef::USERType
uint32_t USERType
Definition stm32h7xx_hal_flash_ex.h:87
FLASH_OBProgramInitTypeDef::CM4BootAddr1
uint32_t CM4BootAddr1
Definition stm32h7xx_hal_flash_ex.h:122
FLASH_OBProgramInitTypeDef::SecureAreaEndAddr
uint32_t SecureAreaEndAddr
Definition stm32h7xx_hal_flash_ex.h:133
FLASH_OBProgramInitTypeDef::BootConfig
uint32_t BootConfig
Definition stm32h7xx_hal_flash_ex.h:106
FLASH_OBProgramInitTypeDef::PCROPStartAddr
uint32_t PCROPStartAddr
Definition stm32h7xx_hal_flash_ex.h:100
FLASH_OBProgramInitTypeDef::PCROPEndAddr
uint32_t PCROPEndAddr
Definition stm32h7xx_hal_flash_ex.h:103
FLASH_OBProgramInitTypeDef::CM4BootAddr0
uint32_t CM4BootAddr0
Definition stm32h7xx_hal_flash_ex.h:119
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