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Data Structures | Enumerator | Variables
Edma

Data Structures

struct  _edma_config
 eDMA global configuration structure. More...
 
struct  _edma_transfer_config
 eDMA transfer configuration More...
 
struct  _edma_channel_Preemption_config
 eDMA channel priority configuration More...
 
struct  _edma_minor_offset_config
 eDMA minor offset configuration More...
 
struct  _edma_tcd
 eDMA TCD. More...
 
struct  _edma_handle
 eDMA transfer handle structure More...
 

Variables

bool _edma_config::enableContinuousLinkMode
 
bool _edma_config::enableHaltOnError
 
bool _edma_config::enableRoundRobinArbitration
 
bool _edma_config::enableDebugMode
 
uint32_t _edma_transfer_config::srcAddr
 
uint32_t _edma_transfer_config::destAddr
 
edma_transfer_size_t _edma_transfer_config::srcTransferSize
 
edma_transfer_size_t _edma_transfer_config::destTransferSize
 
int16_t _edma_transfer_config::srcOffset
 
int16_t _edma_transfer_config::destOffset
 
uint32_t _edma_transfer_config::minorLoopBytes
 
uint32_t _edma_transfer_config::majorLoopCounts
 
bool _edma_channel_Preemption_config::enableChannelPreemption
 
bool _edma_channel_Preemption_config::enablePreemptAbility
 
uint8_t _edma_channel_Preemption_config::channelPriority
 
bool _edma_minor_offset_config::enableSrcMinorOffset
 
bool _edma_minor_offset_config::enableDestMinorOffset
 
uint32_t _edma_minor_offset_config::minorOffset
 
__IO uint32_t _edma_tcd::SADDR
 
__IO uint16_t _edma_tcd::SOFF
 
__IO uint16_t _edma_tcd::ATTR
 
__IO uint32_t _edma_tcd::NBYTES
 
__IO uint32_t _edma_tcd::SLAST
 
__IO uint32_t _edma_tcd::DADDR
 
__IO uint16_t _edma_tcd::DOFF
 
__IO uint16_t _edma_tcd::CITER
 
__IO uint32_t _edma_tcd::DLAST_SGA
 
__IO uint16_t _edma_tcd::CSR
 
__IO uint16_t _edma_tcd::BITER
 
edma_callback _edma_handle::callback
 
void * _edma_handle::userData
 
DMA_Type * _edma_handle::base
 
edma_tcd_t_edma_handle::tcdPool
 
uint8_t _edma_handle::channel
 
volatile int8_t _edma_handle::header
 
volatile int8_t _edma_handle::tail
 
volatile int8_t _edma_handle::tcdUsed
 
volatile int8_t _edma_handle::tcdSize
 
uint8_t _edma_handle::flags
 

Driver version

enum  _edma_transfer_size {
  kEDMA_TransferSize1Bytes = 0x0U , kEDMA_TransferSize2Bytes = 0x1U , kEDMA_TransferSize4Bytes = 0x2U , kEDMA_TransferSize8Bytes = 0x3U ,
  kEDMA_TransferSize16Bytes = 0x4U , kEDMA_TransferSize32Bytes = 0x5U
}
 eDMA transfer configuration More...
 
enum  _edma_modulo {
  kEDMA_ModuloDisable = 0x0U , kEDMA_Modulo2bytes , kEDMA_Modulo4bytes , kEDMA_Modulo8bytes ,
  kEDMA_Modulo16bytes , kEDMA_Modulo32bytes , kEDMA_Modulo64bytes , kEDMA_Modulo128bytes ,
  kEDMA_Modulo256bytes , kEDMA_Modulo512bytes , kEDMA_Modulo1Kbytes , kEDMA_Modulo2Kbytes ,
  kEDMA_Modulo4Kbytes , kEDMA_Modulo8Kbytes , kEDMA_Modulo16Kbytes , kEDMA_Modulo32Kbytes ,
  kEDMA_Modulo64Kbytes , kEDMA_Modulo128Kbytes , kEDMA_Modulo256Kbytes , kEDMA_Modulo512Kbytes ,
  kEDMA_Modulo1Mbytes , kEDMA_Modulo2Mbytes , kEDMA_Modulo4Mbytes , kEDMA_Modulo8Mbytes ,
  kEDMA_Modulo16Mbytes , kEDMA_Modulo32Mbytes , kEDMA_Modulo64Mbytes , kEDMA_Modulo128Mbytes ,
  kEDMA_Modulo256Mbytes , kEDMA_Modulo512Mbytes , kEDMA_Modulo1Gbytes , kEDMA_Modulo2Gbytes
}
 eDMA modulo configuration More...
 
enum  _edma_bandwidth { kEDMA_BandwidthStallNone = 0x0U , kEDMA_BandwidthStall4Cycle = 0x2U , kEDMA_BandwidthStall8Cycle = 0x3U }
 Bandwidth control. More...
 
enum  _edma_channel_link_type { kEDMA_LinkNone = 0x0U , kEDMA_MinorLink , kEDMA_MajorLink }
 Channel link type. More...
 
enum  _edma_channel_status_flags { kEDMA_DoneFlag = 0x1U , kEDMA_ErrorFlag = 0x2U , kEDMA_InterruptFlag = 0x4U }
 eDMA channel status flags. More...
 
enum  _edma_error_status_flags {
  kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK , kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK , kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK , kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK ,
  kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK , kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK , kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK , kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK ,
  kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK , kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK , kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK , kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK ,
  kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK
}
 eDMA channel error status flags. More...
 
enum  _edma_interrupt_enable { kEDMA_ErrorInterruptEnable = 0x1U , kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK , kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK }
 eDMA interrupt source More...
 
enum  _edma_transfer_type { kEDMA_MemoryToMemory = 0x0U , kEDMA_PeripheralToMemory , kEDMA_MemoryToPeripheral }
 eDMA transfer type More...
 
enum  _edma_transfer_status { kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0) , kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1) }
 eDMA transfer status More...
 
typedef enum _edma_transfer_size edma_transfer_size_t
 eDMA transfer configuration
 
typedef enum _edma_modulo edma_modulo_t
 eDMA modulo configuration
 
typedef enum _edma_bandwidth edma_bandwidth_t
 Bandwidth control.
 
typedef enum _edma_channel_link_type edma_channel_link_type_t
 Channel link type.
 
typedef enum _edma_interrupt_enable edma_interrupt_enable_t
 eDMA interrupt source
 
typedef enum _edma_transfer_type edma_transfer_type_t
 eDMA transfer type
 
typedef struct _edma_config edma_config_t
 eDMA global configuration structure.
 
typedef struct _edma_transfer_config edma_transfer_config_t
 eDMA transfer configuration
 
typedef struct _edma_channel_Preemption_config edma_channel_Preemption_config_t
 eDMA channel priority configuration
 
typedef struct _edma_minor_offset_config edma_minor_offset_config_t
 eDMA minor offset configuration
 
typedef struct _edma_tcd edma_tcd_t
 eDMA TCD.
 
typedef void(* edma_callback) (struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)
 Define callback function for eDMA.
 
typedef struct _edma_handle edma_handle_t
 eDMA transfer handle structure
 

eDMA initialization and de-initialization

void EDMA_Init (DMA_Type *base, const edma_config_t *config)
 Initializes the eDMA peripheral.
 
void EDMA_Deinit (DMA_Type *base)
 Deinitializes the eDMA peripheral.
 
void EDMA_InstallTCD (DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
 Push content of TCD structure into hardware TCD register.
 
void EDMA_GetDefaultConfig (edma_config_t *config)
 Gets the eDMA default configuration structure.
 

eDMA Channel Operation

void EDMA_ResetChannel (DMA_Type *base, uint32_t channel)
 Sets all TCD registers to default values.
 
void EDMA_SetTransferConfig (DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
 Configures the eDMA transfer attribute.
 
void EDMA_SetMinorOffsetConfig (DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
 Configures the eDMA minor offset feature.
 
static void EDMA_SetChannelPreemptionConfig (DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config)
 Configures the eDMA channel preemption feature.
 
void EDMA_SetChannelLink (DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
 Sets the channel link for the eDMA transfer.
 
void EDMA_SetBandWidth (DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
 Sets the bandwidth for the eDMA transfer.
 
void EDMA_SetModulo (DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
 Sets the source modulo and the destination modulo for the eDMA transfer.
 
static void EDMA_EnableAsyncRequest (DMA_Type *base, uint32_t channel, bool enable)
 Enables an async request for the eDMA transfer.
 
static void EDMA_EnableAutoStopRequest (DMA_Type *base, uint32_t channel, bool enable)
 Enables an auto stop request for the eDMA transfer.
 
void EDMA_EnableChannelInterrupts (DMA_Type *base, uint32_t channel, uint32_t mask)
 Enables the interrupt source for the eDMA transfer.
 
void EDMA_DisableChannelInterrupts (DMA_Type *base, uint32_t channel, uint32_t mask)
 Disables the interrupt source for the eDMA transfer.
 

eDMA TCD Operation

void EDMA_TcdReset (edma_tcd_t *tcd)
 Sets all fields to default values for the TCD structure.
 
void EDMA_TcdSetTransferConfig (edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
 Configures the eDMA TCD transfer attribute.
 
void EDMA_TcdSetMinorOffsetConfig (edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
 Configures the eDMA TCD minor offset feature.
 
void EDMA_TcdSetChannelLink (edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
 Sets the channel link for the eDMA TCD.
 
static void EDMA_TcdSetBandWidth (edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
 Sets the bandwidth for the eDMA TCD.
 
void EDMA_TcdSetModulo (edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
 Sets the source modulo and the destination modulo for the eDMA TCD.
 
static void EDMA_TcdEnableAutoStopRequest (edma_tcd_t *tcd, bool enable)
 Sets the auto stop request for the eDMA TCD.
 
void EDMA_TcdEnableInterrupts (edma_tcd_t *tcd, uint32_t mask)
 Enables the interrupt source for the eDMA TCD.
 
void EDMA_TcdDisableInterrupts (edma_tcd_t *tcd, uint32_t mask)
 Disables the interrupt source for the eDMA TCD.
 

eDMA Channel Transfer Operation

static void EDMA_EnableChannelRequest (DMA_Type *base, uint32_t channel)
 Enables the eDMA hardware channel request.
 
static void EDMA_DisableChannelRequest (DMA_Type *base, uint32_t channel)
 Disables the eDMA hardware channel request.
 
static void EDMA_TriggerChannelStart (DMA_Type *base, uint32_t channel)
 Starts the eDMA transfer by using the software trigger.
 

eDMA Channel Status Operation

uint32_t EDMA_GetRemainingMajorLoopCount (DMA_Type *base, uint32_t channel)
 Gets the remaining major loop count from the eDMA current channel TCD.
 
static uint32_t EDMA_GetErrorStatusFlags (DMA_Type *base)
 Gets the eDMA channel error status flags.
 
uint32_t EDMA_GetChannelStatusFlags (DMA_Type *base, uint32_t channel)
 Gets the eDMA channel status flags.
 
void EDMA_ClearChannelStatusFlags (DMA_Type *base, uint32_t channel, uint32_t mask)
 Clears the eDMA channel status flags.
 

eDMA Transactional Operation

void EDMA_CreateHandle (edma_handle_t *handle, DMA_Type *base, uint32_t channel)
 Creates the eDMA handle.
 
void EDMA_InstallTCDMemory (edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
 Installs the TCDs memory pool into the eDMA handle.
 
void EDMA_SetCallback (edma_handle_t *handle, edma_callback callback, void *userData)
 Installs a callback function for the eDMA transfer.
 
void EDMA_PrepareTransfer (edma_transfer_config_t *config, void *srcAddr, uint32_t srcWidth, void *destAddr, uint32_t destWidth, uint32_t bytesEachRequest, uint32_t transferBytes, edma_transfer_type_t type)
 Prepares the eDMA transfer structure.
 
status_t EDMA_SubmitTransfer (edma_handle_t *handle, const edma_transfer_config_t *config)
 Submits the eDMA transfer request.
 
void EDMA_StartTransfer (edma_handle_t *handle)
 eDMA starts transfer.
 
void EDMA_StopTransfer (edma_handle_t *handle)
 eDMA stops transfer.
 
void EDMA_AbortTransfer (edma_handle_t *handle)
 eDMA aborts transfer.
 
static uint32_t EDMA_GetUnusedTCDNumber (edma_handle_t *handle)
 Get unused TCD slot number.
 
static uint32_t EDMA_GetNextTCDAddress (edma_handle_t *handle)
 Get the next tcd address.
 
void EDMA_HandleIRQ (edma_handle_t *handle)
 eDMA IRQ handler for the current major loop transfer completion.
 

Detailed Description

Typedef Documentation

◆ edma_bandwidth_t

Bandwidth control.

◆ edma_callback

typedef void(* edma_callback) (struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds)

Define callback function for eDMA.

This callback function is called in the EDMA interrupt handle. In normal mode, run into callback function means the transfer users need is done. In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.

Parameters
handleEDMA handle pointer, users shall not touch the values inside.
userDataThe callback user parameter pointer. Users can use this parameter to involve things users need to change in EDMA callback function.
transferDoneIf the current loaded transfer done. In normal mode it means if all transfer done. In scatter gather mode, this parameter shows is the current transfer block in EDMA register is done. As the load of core is different, it will be different if the new tcd loaded into EDMA registers while this callback called. If true, it always means new tcd still not loaded into registers, while false means new tcd already loaded into registers.
tcdsHow many tcds are done from the last callback. This parameter only used in scatter gather mode. It tells user how many tcds are finished between the last callback and this.

Definition at line 242 of file fsl_edma.h.

◆ edma_channel_link_type_t

Channel link type.

◆ edma_channel_Preemption_config_t

eDMA channel priority configuration

◆ edma_config_t

typedef struct _edma_config edma_config_t

eDMA global configuration structure.

◆ edma_handle_t

typedef struct _edma_handle edma_handle_t

eDMA transfer handle structure

◆ edma_interrupt_enable_t

eDMA interrupt source

◆ edma_minor_offset_config_t

eDMA minor offset configuration

◆ edma_modulo_t

eDMA modulo configuration

◆ edma_tcd_t

typedef struct _edma_tcd edma_tcd_t

eDMA TCD.

This structure is same as TCD register which is described in reference manual, and is used to configure the scatter/gather feature as a next hardware TCD.

◆ edma_transfer_config_t

eDMA transfer configuration

This structure configures the source/destination transfer attribute.

◆ edma_transfer_size_t

eDMA transfer configuration

◆ edma_transfer_type_t

eDMA transfer type

Enumeration Type Documentation

◆ _edma_bandwidth

Bandwidth control.

Enumerator
kEDMA_BandwidthStallNone 

No eDMA engine stalls.

kEDMA_BandwidthStall4Cycle 

eDMA engine stalls for 4 cycles after each read/write.

kEDMA_BandwidthStall8Cycle 

eDMA engine stalls for 8 cycles after each read/write.

Definition at line 84 of file fsl_edma.h.

85{
86 kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */
87 kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */
88 kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */
enum _edma_bandwidth edma_bandwidth_t
Bandwidth control.
@ kEDMA_BandwidthStall4Cycle
Definition fsl_edma.h:87
@ kEDMA_BandwidthStall8Cycle
Definition fsl_edma.h:88
@ kEDMA_BandwidthStallNone
Definition fsl_edma.h:86

◆ _edma_channel_link_type

Channel link type.

Enumerator
kEDMA_LinkNone 

No channel link

kEDMA_MinorLink 

Channel link after each minor loop

kEDMA_MajorLink 

Channel link while major loop count exhausted

Definition at line 92 of file fsl_edma.h.

93{
94 kEDMA_LinkNone = 0x0U, /*!< No channel link */
95 kEDMA_MinorLink, /*!< Channel link after each minor loop */
96 kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */
enum _edma_channel_link_type edma_channel_link_type_t
Channel link type.
@ kEDMA_MinorLink
Definition fsl_edma.h:95
@ kEDMA_MajorLink
Definition fsl_edma.h:96
@ kEDMA_LinkNone
Definition fsl_edma.h:94

◆ _edma_channel_status_flags

eDMA channel status flags.

Enumerator
kEDMA_DoneFlag 

DONE flag, set while transfer finished, CITER value exhausted

kEDMA_ErrorFlag 

eDMA error flag, an error occurred in a transfer

kEDMA_InterruptFlag 

eDMA interrupt flag, set while an interrupt occurred of this channel

Definition at line 100 of file fsl_edma.h.

101{
102 kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/
103 kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */
104 kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */
105};
@ kEDMA_ErrorFlag
Definition fsl_edma.h:103
@ kEDMA_DoneFlag
Definition fsl_edma.h:102
@ kEDMA_InterruptFlag
Definition fsl_edma.h:104

◆ _edma_error_status_flags

eDMA channel error status flags.

Enumerator
kEDMA_DestinationBusErrorFlag 

Bus error on destination address

kEDMA_SourceBusErrorFlag 

Bus error on the source address

kEDMA_ScatterGatherErrorFlag 

Error on the Scatter/Gather address, not 32byte aligned.

kEDMA_NbytesErrorFlag 

NBYTES/CITER configuration error

kEDMA_DestinationOffsetErrorFlag 

Destination offset not aligned with destination size

kEDMA_DestinationAddressErrorFlag 

Destination address not aligned with destination size

kEDMA_SourceOffsetErrorFlag 

Source offset not aligned with source size

kEDMA_SourceAddressErrorFlag 

Source address not aligned with source size

kEDMA_ErrorChannelFlag 

Error channel number of the cancelled channel number

kEDMA_ChannelPriorityErrorFlag 

Channel priority is not unique.

kEDMA_TransferCanceledFlag 

Transfer cancelled

kEDMA_GroupPriorityErrorFlag 

Group priority is not unique.

kEDMA_ValidFlag 

No error occurred, this bit is 0. Otherwise, it is 1.

Definition at line 108 of file fsl_edma.h.

109{
110 kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */
111 kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */
112 kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */
113 kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */
114 kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */
115 kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */
116 kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */
117 kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/
118 kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */
119 kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */
120 kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */
121#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
122 kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
123#endif
124 kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
125};
@ kEDMA_TransferCanceledFlag
Definition fsl_edma.h:120
@ kEDMA_GroupPriorityErrorFlag
Definition fsl_edma.h:122
@ kEDMA_ErrorChannelFlag
Definition fsl_edma.h:118
@ kEDMA_SourceAddressErrorFlag
Definition fsl_edma.h:117
@ kEDMA_DestinationBusErrorFlag
Definition fsl_edma.h:110
@ kEDMA_SourceBusErrorFlag
Definition fsl_edma.h:111
@ kEDMA_ChannelPriorityErrorFlag
Definition fsl_edma.h:119
@ kEDMA_ScatterGatherErrorFlag
Definition fsl_edma.h:112
@ kEDMA_DestinationOffsetErrorFlag
Definition fsl_edma.h:114
@ kEDMA_ValidFlag
Definition fsl_edma.h:124
@ kEDMA_NbytesErrorFlag
Definition fsl_edma.h:113
@ kEDMA_SourceOffsetErrorFlag
Definition fsl_edma.h:116
@ kEDMA_DestinationAddressErrorFlag
Definition fsl_edma.h:115

◆ _edma_interrupt_enable

eDMA interrupt source

Enumerator
kEDMA_ErrorInterruptEnable 

Enable interrupt while channel error occurs.

kEDMA_MajorInterruptEnable 

Enable interrupt while major count exhausted.

kEDMA_HalfInterruptEnable 

Enable interrupt while major count to half value.

Definition at line 128 of file fsl_edma.h.

129{
130 kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */
131 kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */
132 kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */
enum _edma_interrupt_enable edma_interrupt_enable_t
eDMA interrupt source
@ kEDMA_MajorInterruptEnable
Definition fsl_edma.h:131
@ kEDMA_HalfInterruptEnable
Definition fsl_edma.h:132
@ kEDMA_ErrorInterruptEnable
Definition fsl_edma.h:130

◆ _edma_modulo

eDMA modulo configuration

Enumerator
kEDMA_ModuloDisable 

Disable modulo

kEDMA_Modulo2bytes 

Circular buffer size is 2 bytes.

kEDMA_Modulo4bytes 

Circular buffer size is 4 bytes.

kEDMA_Modulo8bytes 

Circular buffer size is 8 bytes.

kEDMA_Modulo16bytes 

Circular buffer size is 16 bytes.

kEDMA_Modulo32bytes 

Circular buffer size is 32 bytes.

kEDMA_Modulo64bytes 

Circular buffer size is 64 bytes.

kEDMA_Modulo128bytes 

Circular buffer size is 128 bytes.

kEDMA_Modulo256bytes 

Circular buffer size is 256 bytes.

kEDMA_Modulo512bytes 

Circular buffer size is 512 bytes.

kEDMA_Modulo1Kbytes 

Circular buffer size is 1 K bytes.

kEDMA_Modulo2Kbytes 

Circular buffer size is 2 K bytes.

kEDMA_Modulo4Kbytes 

Circular buffer size is 4 K bytes.

kEDMA_Modulo8Kbytes 

Circular buffer size is 8 K bytes.

kEDMA_Modulo16Kbytes 

Circular buffer size is 16 K bytes.

kEDMA_Modulo32Kbytes 

Circular buffer size is 32 K bytes.

kEDMA_Modulo64Kbytes 

Circular buffer size is 64 K bytes.

kEDMA_Modulo128Kbytes 

Circular buffer size is 128 K bytes.

kEDMA_Modulo256Kbytes 

Circular buffer size is 256 K bytes.

kEDMA_Modulo512Kbytes 

Circular buffer size is 512 K bytes.

kEDMA_Modulo1Mbytes 

Circular buffer size is 1 M bytes.

kEDMA_Modulo2Mbytes 

Circular buffer size is 2 M bytes.

kEDMA_Modulo4Mbytes 

Circular buffer size is 4 M bytes.

kEDMA_Modulo8Mbytes 

Circular buffer size is 8 M bytes.

kEDMA_Modulo16Mbytes 

Circular buffer size is 16 M bytes.

kEDMA_Modulo32Mbytes 

Circular buffer size is 32 M bytes.

kEDMA_Modulo64Mbytes 

Circular buffer size is 64 M bytes.

kEDMA_Modulo128Mbytes 

Circular buffer size is 128 M bytes.

kEDMA_Modulo256Mbytes 

Circular buffer size is 256 M bytes.

kEDMA_Modulo512Mbytes 

Circular buffer size is 512 M bytes.

kEDMA_Modulo1Gbytes 

Circular buffer size is 1 G bytes.

kEDMA_Modulo2Gbytes 

Circular buffer size is 2 G bytes.

Definition at line 47 of file fsl_edma.h.

48{
49 kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */
50 kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */
51 kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */
52 kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */
53 kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */
54 kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */
55 kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */
56 kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */
57 kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */
58 kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */
59 kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */
60 kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */
61 kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */
62 kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */
63 kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */
64 kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */
65 kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */
66 kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */
67 kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */
68 kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */
69 kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */
70 kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */
71 kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */
72 kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */
73 kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */
74 kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */
75 kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */
76 kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */
77 kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */
78 kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */
79 kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */
80 kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */
enum _edma_modulo edma_modulo_t
eDMA modulo configuration
@ kEDMA_Modulo128Mbytes
Definition fsl_edma.h:76
@ kEDMA_Modulo512Mbytes
Definition fsl_edma.h:78
@ kEDMA_Modulo1Gbytes
Definition fsl_edma.h:79
@ kEDMA_Modulo4bytes
Definition fsl_edma.h:51
@ kEDMA_Modulo16Mbytes
Definition fsl_edma.h:73
@ kEDMA_Modulo1Mbytes
Definition fsl_edma.h:69
@ kEDMA_Modulo4Mbytes
Definition fsl_edma.h:71
@ kEDMA_Modulo256Mbytes
Definition fsl_edma.h:77
@ kEDMA_Modulo8Kbytes
Definition fsl_edma.h:62
@ kEDMA_Modulo512bytes
Definition fsl_edma.h:58
@ kEDMA_Modulo2Mbytes
Definition fsl_edma.h:70
@ kEDMA_Modulo16Kbytes
Definition fsl_edma.h:63
@ kEDMA_Modulo1Kbytes
Definition fsl_edma.h:59
@ kEDMA_Modulo8bytes
Definition fsl_edma.h:52
@ kEDMA_Modulo64Kbytes
Definition fsl_edma.h:65
@ kEDMA_Modulo2Gbytes
Definition fsl_edma.h:80
@ kEDMA_Modulo256bytes
Definition fsl_edma.h:57
@ kEDMA_ModuloDisable
Definition fsl_edma.h:49
@ kEDMA_Modulo16bytes
Definition fsl_edma.h:53
@ kEDMA_Modulo128bytes
Definition fsl_edma.h:56
@ kEDMA_Modulo32bytes
Definition fsl_edma.h:54
@ kEDMA_Modulo2Kbytes
Definition fsl_edma.h:60
@ kEDMA_Modulo8Mbytes
Definition fsl_edma.h:72
@ kEDMA_Modulo32Mbytes
Definition fsl_edma.h:74
@ kEDMA_Modulo256Kbytes
Definition fsl_edma.h:67
@ kEDMA_Modulo4Kbytes
Definition fsl_edma.h:61
@ kEDMA_Modulo64Mbytes
Definition fsl_edma.h:75
@ kEDMA_Modulo32Kbytes
Definition fsl_edma.h:64
@ kEDMA_Modulo64bytes
Definition fsl_edma.h:55
@ kEDMA_Modulo2bytes
Definition fsl_edma.h:50
@ kEDMA_Modulo128Kbytes
Definition fsl_edma.h:66
@ kEDMA_Modulo512Kbytes
Definition fsl_edma.h:68

◆ _edma_transfer_size

eDMA transfer configuration

Enumerator
kEDMA_TransferSize1Bytes 

Source/Destination data transfer size is 1 byte every time

kEDMA_TransferSize2Bytes 

Source/Destination data transfer size is 2 bytes every time

kEDMA_TransferSize4Bytes 

Source/Destination data transfer size is 4 bytes every time

kEDMA_TransferSize8Bytes 

Source/Destination data transfer size is 8 bytes every time

kEDMA_TransferSize16Bytes 

Source/Destination data transfer size is 16 bytes every time

kEDMA_TransferSize32Bytes 

Source/Destination data transfer size is 32 bytes every time

Definition at line 36 of file fsl_edma.h.

37{
38 kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */
39 kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */
40 kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */
41 kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */
42 kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
43 kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
enum _edma_transfer_size edma_transfer_size_t
eDMA transfer configuration
@ kEDMA_TransferSize16Bytes
Definition fsl_edma.h:42
@ kEDMA_TransferSize8Bytes
Definition fsl_edma.h:41
@ kEDMA_TransferSize4Bytes
Definition fsl_edma.h:40
@ kEDMA_TransferSize2Bytes
Definition fsl_edma.h:39
@ kEDMA_TransferSize1Bytes
Definition fsl_edma.h:38
@ kEDMA_TransferSize32Bytes
Definition fsl_edma.h:43

◆ _edma_transfer_status

eDMA transfer status

Enumerator
kStatus_EDMA_QueueFull 

TCD queue is full.

kStatus_EDMA_Busy 

Channel is busy and can't handle the transfer request.

Definition at line 144 of file fsl_edma.h.

145{
146 kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */
147 kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the
148 transfer request. */
149};
@ kStatus_EDMA_QueueFull
Definition fsl_edma.h:146
@ kStatus_EDMA_Busy
Definition fsl_edma.h:147
@ kStatusGroup_EDMA
Definition fsl_common.h:100

◆ _edma_transfer_type

eDMA transfer type

Enumerator
kEDMA_MemoryToMemory 

Transfer from memory to memory

kEDMA_PeripheralToMemory 

Transfer from peripheral to memory

kEDMA_MemoryToPeripheral 

Transfer from memory to peripheral

Definition at line 136 of file fsl_edma.h.

137{
138 kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */
139 kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */
140 kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */
enum _edma_transfer_type edma_transfer_type_t
eDMA transfer type
@ kEDMA_PeripheralToMemory
Definition fsl_edma.h:139
@ kEDMA_MemoryToPeripheral
Definition fsl_edma.h:140
@ kEDMA_MemoryToMemory
Definition fsl_edma.h:138

Function Documentation

◆ EDMA_AbortTransfer()

void EDMA_AbortTransfer ( edma_handle_t handle)

eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

Parameters
handleDMA handle pointer.

brief eDMA aborts transfer.

This function disables the channel request and clear transfer status bits. Users can submit another transfer after calling this API.

param handle DMA handle pointer.

Definition at line 1164 of file fsl_edma.c.

1165{
1166 handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
1167 /*
1168 Clear CSR to release channel. Because if the given channel started transfer,
1169 CSR will be not zero. Because if it is the last transfer, DREQ will be set.
1170 If not, ESG will be set.
1171 */
1172 handle->base->TCD[handle->channel].CSR = 0;
1173 /* Cancel all next TCD transfer. */
1174 handle->base->TCD[handle->channel].DLAST_SGA = 0;
1175
1176 /* Handle the tcd */
1177 if (handle->tcdPool != NULL)
1178 {
1179 handle->header = 0;
1180 handle->tail = 0;
1181 handle->tcdUsed = 0;
1182 }
1183}
DMA_Type * base
Definition fsl_edma.h:249
volatile int8_t header
Definition fsl_edma.h:252
volatile int8_t tcdUsed
Definition fsl_edma.h:254
edma_tcd_t * tcdPool
Definition fsl_edma.h:250
uint8_t channel
Definition fsl_edma.h:251
volatile int8_t tail
Definition fsl_edma.h:253

Referenced by LPSPI_MasterTransferAbortEDMA(), LPSPI_SlaveTransferAbortEDMA(), LPUART_TransferAbortReceiveEDMA(), and LPUART_TransferAbortSendEDMA().

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◆ EDMA_ClearChannelStatusFlags()

void EDMA_ClearChannelStatusFlags ( DMA_Type *  base,
uint32_t  channel,
uint32_t  mask 
)

Clears the eDMA channel status flags.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
maskThe mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

brief Clears the eDMA channel status flags.

param base eDMA peripheral base address. param channel eDMA channel number. param mask The mask of channel status to be cleared. Users need to use the defined _edma_channel_status_flags type.

Definition at line 708 of file fsl_edma.c.

709{
710 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
711
712 /* Clear DONE bit flag */
713 if (mask & kEDMA_DoneFlag)
714 {
715 base->CDNE = channel;
716 }
717 /* Clear ERROR bit flag */
718 if (mask & kEDMA_ErrorFlag)
719 {
720 base->CERR = channel;
721 }
722 /* Clear INT bit flag */
723 if (mask & kEDMA_InterruptFlag)
724 {
725 base->CINT = channel;
726 }
727}
uint16_t channel
Definition adc_inputs.h:104

◆ EDMA_CreateHandle()

void EDMA_CreateHandle ( edma_handle_t handle,
DMA_Type *  base,
uint32_t  channel 
)

Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

Parameters
handleeDMA handle pointer. The eDMA handle stores callback function and parameters.
baseeDMA peripheral base address.
channeleDMA channel number.

brief Creates the eDMA handle.

This function is called if using the transactional API for eDMA. This function initializes the internal state of the eDMA handle.

param handle eDMA handle pointer. The eDMA handle stores callback function and parameters. param base eDMA peripheral base address. param channel eDMA channel number.

Definition at line 757 of file fsl_edma.c.

758{
759 assert(handle != NULL);
760 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
761
762 uint32_t edmaInstance;
763 uint32_t channelIndex;
764 uint8_t StartInstance;
765 edma_tcd_t *tcdRegs;
766
767 /* Zero the handle */
768 memset(handle, 0, sizeof(*handle));
769
770 handle->base = base;
771 handle->channel = channel;
772 /* Get the DMA instance number */
773 edmaInstance = EDMA_GetInstance(base);
774 StartInstance = Get_StartInstance();
775 channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
776 s_EDMAHandle[channelIndex] = handle;
777
778 /* Enable NVIC interrupt */
779 EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
780
781 /*
782 Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
783 CSR will be 0. Because in order to suit EDMA busy check mechanism in
784 EDMA_SubmitTransfer, CSR must be set 0.
785 */
786 tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
787 tcdRegs->SADDR = 0;
788 tcdRegs->SOFF = 0;
789 tcdRegs->ATTR = 0;
790 tcdRegs->NBYTES = 0;
791 tcdRegs->SLAST = 0;
792 tcdRegs->DADDR = 0;
793 tcdRegs->DOFF = 0;
794 tcdRegs->CITER = 0;
795 tcdRegs->DLAST_SGA = 0;
796 tcdRegs->CSR = 0;
797 tcdRegs->BITER = 0;
798}
static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL]
Array to map EDMA instance number to IRQ number.
Definition fsl_edma.c:47
static edma_handle_t * s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL *FSL_FEATURE_SOC_EDMA_COUNT]
Pointers to transfer handle for each EDMA channel.
Definition fsl_edma.c:50
static uint32_t EDMA_GetInstance(DMA_Type *base)
Get instance number for EDMA.
Definition fsl_edma.c:56
static uint8_t Get_StartInstance(void)
Definition fsl_edma.c:729
__IO uint32_t DADDR
Definition fsl_edma.h:213
__IO uint16_t CSR
Definition fsl_edma.h:217
__IO uint16_t BITER
Definition fsl_edma.h:218
__IO uint32_t SLAST
Definition fsl_edma.h:212
__IO uint32_t DLAST_SGA
Definition fsl_edma.h:216
__IO uint16_t CITER
Definition fsl_edma.h:215
__IO uint32_t SADDR
Definition fsl_edma.h:208
__IO uint16_t DOFF
Definition fsl_edma.h:214
__IO uint16_t SOFF
Definition fsl_edma.h:209
__IO uint32_t NBYTES
Definition fsl_edma.h:211
__IO uint16_t ATTR
Definition fsl_edma.h:210
eDMA TCD.
Definition fsl_edma.h:207

Referenced by uart_lld_start().

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◆ EDMA_Deinit()

void EDMA_Deinit ( DMA_Type *  base)

Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

Parameters
baseeDMA peripheral base address.

brief Deinitializes the eDMA peripheral.

This function gates the eDMA clock.

param base eDMA peripheral base address.

Definition at line 143 of file fsl_edma.c.

144{
145#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
146 /* Gate EDMA peripheral clock */
148#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
149}
static const clock_ip_name_t s_edmaClockName[]
Array to map EDMA instance number to clock name.
Definition fsl_edma.c:43
static void CLOCK_DisableClock(clock_ip_name_t name)
Disable the clock for specific IP.
Definition fsl_clock.h:653
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◆ EDMA_DisableChannelInterrupts()

void EDMA_DisableChannelInterrupts ( DMA_Type *  base,
uint32_t  channel,
uint32_t  mask 
)

Disables the interrupt source for the eDMA transfer.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
maskThe mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

brief Disables the interrupt source for the eDMA transfer.

param base eDMA peripheral base address. param channel eDMA channel number. param mask The mask of the interrupt source to be set. Use the defined edma_interrupt_enable_t type.

Definition at line 361 of file fsl_edma.c.

362{
363 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
364
365 /* Disable error interrupt */
367 {
368 base->EEI &= ~(0x1U << channel);
369 }
370
371 /* Disable Major interrupt */
373 {
374 base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
375 }
376
377 /* Disable Half major interrupt */
378 if (mask & kEDMA_HalfInterruptEnable)
379 {
380 base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
381 }
382}

◆ EDMA_DisableChannelRequest()

static void EDMA_DisableChannelRequest ( DMA_Type *  base,
uint32_t  channel 
)
inlinestatic

Disables the eDMA hardware channel request.

This function disables the hardware channel request.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.

Definition at line 669 of file fsl_edma.h.

670{
671 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
672
673 base->CERQ = DMA_CERQ_CERQ(channel);
674}

◆ EDMA_EnableAsyncRequest()

static void EDMA_EnableAsyncRequest ( DMA_Type *  base,
uint32_t  channel,
bool  enable 
)
inlinestatic

Enables an async request for the eDMA transfer.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
enableThe command to enable (true) or disable (false).

Definition at line 456 of file fsl_edma.h.

457{
458 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
459
460 base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel);
461}
static void enable(const char *param)
Definition settings.cpp:441
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◆ EDMA_EnableAutoStopRequest()

static void EDMA_EnableAutoStopRequest ( DMA_Type *  base,
uint32_t  channel,
bool  enable 
)
inlinestatic

Enables an auto stop request for the eDMA transfer.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
enableThe command to enable (true) or disable (false).

Definition at line 473 of file fsl_edma.h.

474{
475 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
476
477 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
478}
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◆ EDMA_EnableChannelInterrupts()

void EDMA_EnableChannelInterrupts ( DMA_Type *  base,
uint32_t  channel,
uint32_t  mask 
)

Enables the interrupt source for the eDMA transfer.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
maskThe mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

brief Enables the interrupt source for the eDMA transfer.

param base eDMA peripheral base address. param channel eDMA channel number. param mask The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

Definition at line 330 of file fsl_edma.c.

331{
332 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
333
334 /* Enable error interrupt */
336 {
337 base->EEI |= (0x1U << channel);
338 }
339
340 /* Enable Major interrupt */
342 {
343 base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
344 }
345
346 /* Enable Half major interrupt */
347 if (mask & kEDMA_HalfInterruptEnable)
348 {
349 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
350 }
351}

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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◆ EDMA_EnableChannelRequest()

static void EDMA_EnableChannelRequest ( DMA_Type *  base,
uint32_t  channel 
)
inlinestatic

Enables the eDMA hardware channel request.

This function enables the hardware channel request.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.

Definition at line 654 of file fsl_edma.h.

655{
656 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
657
658 base->SERQ = DMA_SERQ_SERQ(channel);
659}

◆ EDMA_GetChannelStatusFlags()

uint32_t EDMA_GetChannelStatusFlags ( DMA_Type *  base,
uint32_t  channel 
)

Gets the eDMA channel status flags.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
Returns
The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

brief Gets the eDMA channel status flags.

param base eDMA peripheral base address. param channel eDMA channel number. return The mask of channel status flags. Users need to use the _edma_channel_status_flags type to decode the return variables.

Definition at line 684 of file fsl_edma.c.

685{
686 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
687
688 uint32_t retval = 0;
689
690 /* Get DONE bit flag */
691 retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
692 /* Get ERROR bit flag */
693 retval |= (((base->ERR >> channel) & 0x1U) << 1U);
694 /* Get INT bit flag */
695 retval |= (((base->INT >> channel) & 0x1U) << 2U);
696
697 return retval;
698}

Referenced by DMA0_04_DriverIRQHandler(), DMA0_08_DriverIRQHandler(), DMA0_0_4_DriverIRQHandler(), DMA0_10_14_DriverIRQHandler(), DMA0_11_15_DriverIRQHandler(), DMA0_15_DriverIRQHandler(), DMA0_16_20_DriverIRQHandler(), DMA0_17_21_DriverIRQHandler(), DMA0_18_22_DriverIRQHandler(), DMA0_19_23_DriverIRQHandler(), DMA0_19_DriverIRQHandler(), DMA0_1_5_DriverIRQHandler(), DMA0_210_DriverIRQHandler(), DMA0_24_28_DriverIRQHandler(), DMA0_25_29_DriverIRQHandler(), DMA0_26_30_DriverIRQHandler(), DMA0_26_DriverIRQHandler(), DMA0_27_31_DriverIRQHandler(), DMA0_2_6_DriverIRQHandler(), DMA0_311_DriverIRQHandler(), DMA0_37_DriverIRQHandler(), DMA0_3_7_DriverIRQHandler(), DMA0_412_DriverIRQHandler(), DMA0_513_DriverIRQHandler(), DMA0_614_DriverIRQHandler(), DMA0_715_DriverIRQHandler(), DMA0_8_12_DriverIRQHandler(), DMA0_9_13_DriverIRQHandler(), DMA0_DMA16_DriverIRQHandler(), DMA10_DMA26_DriverIRQHandler(), DMA11_DMA27_DriverIRQHandler(), DMA12_DMA28_DriverIRQHandler(), DMA13_DMA29_DriverIRQHandler(), DMA14_DMA30_DriverIRQHandler(), DMA15_DMA31_DriverIRQHandler(), DMA1_04_DriverIRQHandler(), DMA1_08_DriverIRQHandler(), DMA1_15_DriverIRQHandler(), DMA1_19_DriverIRQHandler(), DMA1_210_DriverIRQHandler(), DMA1_26_DriverIRQHandler(), DMA1_311_DriverIRQHandler(), DMA1_37_DriverIRQHandler(), DMA1_412_DriverIRQHandler(), DMA1_513_DriverIRQHandler(), DMA1_614_DriverIRQHandler(), DMA1_715_DriverIRQHandler(), DMA1_DMA17_DriverIRQHandler(), DMA2_DMA18_DriverIRQHandler(), DMA3_DMA19_DriverIRQHandler(), DMA4_DMA20_DriverIRQHandler(), DMA5_DMA21_DriverIRQHandler(), DMA6_DMA22_DriverIRQHandler(), DMA7_DMA23_DriverIRQHandler(), DMA8_DMA24_DriverIRQHandler(), and DMA9_DMA25_DriverIRQHandler().

◆ EDMA_GetDefaultConfig()

void EDMA_GetDefaultConfig ( edma_config_t config)

Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values.

config.enableContinuousLinkMode = false;
config.enableHaltOnError = true;
config.enableRoundRobinArbitration = false;
config.enableDebugMode = false;
static constexpr persistent_config_s * config
Parameters
configA pointer to the eDMA configuration structure.

brief Gets the eDMA default configuration structure.

This function sets the configuration structure to default values. The default configuration is set to the following values. code config.enableContinuousLinkMode = false; config.enableHaltOnError = true; config.enableRoundRobinArbitration = false; config.enableDebugMode = false; endcode

param config A pointer to the eDMA configuration structure.

Definition at line 165 of file fsl_edma.c.

166{
167 assert(config != NULL);
168
169 /* Initializes the configure structure to zero. */
170 memset(config, 0, sizeof(*config));
171
172 config->enableRoundRobinArbitration = false;
173 config->enableHaltOnError = true;
174 config->enableContinuousLinkMode = false;
175 config->enableDebugMode = false;
176}

Referenced by dmaInit().

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◆ EDMA_GetErrorStatusFlags()

static uint32_t EDMA_GetErrorStatusFlags ( DMA_Type *  base)
inlinestatic

Gets the eDMA channel error status flags.

Parameters
baseeDMA peripheral base address.
Returns
The mask of error status flags. Users need to use the _edma_error_status_flags type to decode the return variables.

Definition at line 727 of file fsl_edma.h.

728{
729 return base->ES;
730}

◆ EDMA_GetNextTCDAddress()

static uint32_t EDMA_GetNextTCDAddress ( edma_handle_t handle)
inlinestatic

Get the next tcd address.

This function gets the next tcd address. If this is last TCD, return 0.

Parameters
handleDMA handle pointer.
Returns
The next TCD address.

Definition at line 888 of file fsl_edma.h.

889{
890 return (handle->base->TCD[handle->channel].DLAST_SGA);
891}

◆ EDMA_GetRemainingMajorLoopCount()

uint32_t EDMA_GetRemainingMajorLoopCount ( DMA_Type *  base,
uint32_t  channel 
)

Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
Returns
Major loop count which has not been transferred yet for the current TCD.
Note
1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.
  1. The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

brief Gets the remaining major loop count from the eDMA current channel TCD.

This function checks the TCD (Task Control Descriptor) status for a specified eDMA channel and returns the number of major loop count that has not finished.

param base eDMA peripheral base address. param channel eDMA channel number. return Major loop count which has not been transferred yet for the current TCD. note 1. This function can only be used to get unfinished major loop count of transfer without the next TCD, or it might be inaccuracy.

  1. The unfinished/remaining transfer bytes cannot be obtained directly from registers while the channel is running. Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not support getting it while a channel is active. In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine is working with while a channel is running. Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example copied before enabling the channel) is needed. The formula to calculate it is shown below: RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)

Definition at line 648 of file fsl_edma.c.

649{
650 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
651
652 uint32_t remainingCount = 0;
653
654 if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
655 {
656 remainingCount = 0;
657 }
658 else
659 {
660 /* Calculate the unfinished bytes */
661 if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
662 {
663 remainingCount =
664 (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
665 }
666 else
667 {
668 remainingCount =
669 (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
670 }
671 }
672
673 return remainingCount;
674}

Referenced by LPSPI_MasterTransferGetCountEDMA(), LPSPI_SlaveTransferGetCountEDMA(), LPUART_TransferGetReceiveCountEDMA(), and LPUART_TransferGetSendCountEDMA().

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◆ EDMA_GetUnusedTCDNumber()

static uint32_t EDMA_GetUnusedTCDNumber ( edma_handle_t handle)
inlinestatic

Get unused TCD slot number.

This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0.

Parameters
handleDMA handle pointer.
Returns
The unused tcd slot number.

Definition at line 875 of file fsl_edma.h.

876{
877 return (handle->tcdSize - handle->tcdUsed);
878}
volatile int8_t tcdSize
Definition fsl_edma.h:256

◆ EDMA_HandleIRQ()

void EDMA_HandleIRQ ( edma_handle_t handle)

eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for further details.

Parameters
handleeDMA handle pointer.

brief eDMA IRQ handler for the current major loop transfer completion.

This function clears the channel major interrupt flag and calls the callback function if it is not NULL.

Note: For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).

For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have been loaded into the eDMA engine at this point already.).

For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not load a new TCD) from the memory pool to the eDMA engine when major loop completes. Therefore, ensure that the header and tcdUsed updated are identical for them. tcdUsed are both 0 in this case as no TCD to be loaded.

See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for further details.

param handle eDMA handle pointer.

Definition at line 1213 of file fsl_edma.c.

1214{
1215 assert(handle != NULL);
1216
1217 /* Clear EDMA interrupt flag */
1218 handle->base->CINT = handle->channel;
1219 if ((handle->tcdPool == NULL) && (handle->callback != NULL))
1220 {
1221 (handle->callback)(handle, handle->userData, true, 0);
1222 }
1223 else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
1224 {
1225 uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
1226 uint32_t sga_index;
1227 int32_t tcds_done;
1228 uint8_t new_header;
1229 bool transfer_done;
1230
1231 /* Check if transfer is already finished. */
1232 transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
1233 /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */
1234 sga -= (uint32_t)handle->tcdPool;
1235 /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */
1236 sga_index = sga / sizeof(edma_tcd_t);
1237 /* Adjust header positions. */
1238 if (transfer_done)
1239 {
1240 /* New header shall point to the next TCD to be loaded (current one is already finished) */
1241 new_header = sga_index;
1242 }
1243 else
1244 {
1245 /* New header shall point to this descriptor currently loaded (not finished yet) */
1246 new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
1247 }
1248 /* Calculate the number of finished TCDs */
1249 if (new_header == handle->header)
1250 {
1251 if (handle->tcdUsed == handle->tcdSize)
1252 {
1253 tcds_done = handle->tcdUsed;
1254 }
1255 else
1256 {
1257 /* No TCD in the memory are going to be loaded or internal error occurs. */
1258 tcds_done = 0;
1259 }
1260 }
1261 else
1262 {
1263 tcds_done = new_header - handle->header;
1264 if (tcds_done < 0)
1265 {
1266 tcds_done += handle->tcdSize;
1267 }
1268 }
1269 /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
1270 handle->header = new_header;
1271 /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
1272 handle->tcdUsed -= tcds_done;
1273 /* Invoke callback function. */
1274 if (handle->callback)
1275 {
1276 (handle->callback)(handle, handle->userData, transfer_done, tcds_done);
1277 }
1278
1279 /* clear the DONE bit here is meaningful for below cases:
1280 *1.A new TCD has been loaded to EDMA already:
1281 * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten
1282 * if peripheral request isn't coming before next transfer request.
1283 *2.A new TCD has not been loaded to EDMA:
1284 * for the case that transfer request occur in the privious edma callback, this is a case that doesn't
1285 * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD.
1286 */
1287 if (transfer_done)
1288 {
1289 handle->base->CDNE = handle->channel;
1290 }
1291 }
1292}
struct _edma_tcd edma_tcd_t
eDMA TCD.
edma_callback callback
Definition fsl_edma.h:247
void * userData
Definition fsl_edma.h:248

Referenced by DMA0_04_DriverIRQHandler(), DMA0_08_DriverIRQHandler(), DMA0_0_4_DriverIRQHandler(), DMA0_10_14_DriverIRQHandler(), DMA0_11_15_DriverIRQHandler(), DMA0_15_DriverIRQHandler(), DMA0_16_20_DriverIRQHandler(), DMA0_17_21_DriverIRQHandler(), DMA0_18_22_DriverIRQHandler(), DMA0_19_23_DriverIRQHandler(), DMA0_19_DriverIRQHandler(), DMA0_1_5_DriverIRQHandler(), DMA0_210_DriverIRQHandler(), DMA0_24_28_DriverIRQHandler(), DMA0_25_29_DriverIRQHandler(), DMA0_26_30_DriverIRQHandler(), DMA0_26_DriverIRQHandler(), DMA0_27_31_DriverIRQHandler(), DMA0_2_6_DriverIRQHandler(), DMA0_311_DriverIRQHandler(), DMA0_37_DriverIRQHandler(), DMA0_3_7_DriverIRQHandler(), DMA0_412_DriverIRQHandler(), DMA0_513_DriverIRQHandler(), DMA0_614_DriverIRQHandler(), DMA0_715_DriverIRQHandler(), DMA0_8_12_DriverIRQHandler(), DMA0_9_13_DriverIRQHandler(), DMA0_DMA16_DriverIRQHandler(), DMA0_DriverIRQHandler(), DMA10_DMA26_DriverIRQHandler(), DMA10_DriverIRQHandler(), DMA11_DMA27_DriverIRQHandler(), DMA11_DriverIRQHandler(), DMA12_DMA28_DriverIRQHandler(), DMA12_DriverIRQHandler(), DMA13_DMA29_DriverIRQHandler(), DMA13_DriverIRQHandler(), DMA14_DMA30_DriverIRQHandler(), DMA14_DriverIRQHandler(), DMA15_DMA31_DriverIRQHandler(), DMA15_DriverIRQHandler(), DMA16_DriverIRQHandler(), DMA17_DriverIRQHandler(), DMA18_DriverIRQHandler(), DMA19_DriverIRQHandler(), DMA1_04_DriverIRQHandler(), DMA1_08_DriverIRQHandler(), DMA1_15_DriverIRQHandler(), DMA1_19_DriverIRQHandler(), DMA1_210_DriverIRQHandler(), DMA1_26_DriverIRQHandler(), DMA1_311_DriverIRQHandler(), DMA1_37_DriverIRQHandler(), DMA1_412_DriverIRQHandler(), DMA1_513_DriverIRQHandler(), DMA1_614_DriverIRQHandler(), DMA1_715_DriverIRQHandler(), DMA1_DMA17_DriverIRQHandler(), DMA1_DriverIRQHandler(), DMA20_DriverIRQHandler(), DMA21_DriverIRQHandler(), DMA22_DriverIRQHandler(), DMA23_DriverIRQHandler(), DMA24_DriverIRQHandler(), DMA25_DriverIRQHandler(), DMA26_DriverIRQHandler(), DMA27_DriverIRQHandler(), DMA28_DriverIRQHandler(), DMA29_DriverIRQHandler(), DMA2_DMA18_DriverIRQHandler(), DMA2_DriverIRQHandler(), DMA30_DriverIRQHandler(), DMA31_DriverIRQHandler(), DMA3_DMA19_DriverIRQHandler(), DMA3_DriverIRQHandler(), DMA4_DMA20_DriverIRQHandler(), DMA4_DriverIRQHandler(), DMA5_DMA21_DriverIRQHandler(), DMA5_DriverIRQHandler(), DMA6_DMA22_DriverIRQHandler(), DMA6_DriverIRQHandler(), DMA7_DMA23_DriverIRQHandler(), DMA7_DriverIRQHandler(), DMA8_DMA24_DriverIRQHandler(), DMA8_DriverIRQHandler(), DMA9_DMA25_DriverIRQHandler(), and DMA9_DriverIRQHandler().

◆ EDMA_Init()

void EDMA_Init ( DMA_Type *  base,
const edma_config_t config 
)

Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure.

Parameters
baseeDMA peripheral base address.
configA pointer to the configuration structure, see "edma_config_t".
Note
This function enables the minor loop map feature.

brief Initializes the eDMA peripheral.

This function ungates the eDMA clock and configures the eDMA peripheral according to the configuration structure.

param base eDMA peripheral base address. param config A pointer to the configuration structure, see "edma_config_t". note This function enables the minor loop map feature.

Definition at line 113 of file fsl_edma.c.

114{
115 assert(config != NULL);
116
117 uint32_t tmpreg;
118
119#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
120 /* Ungate EDMA peripheral clock */
122#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
123
124 /* clear all the enabled request, status to make sure EDMA status is in normal condition */
125 base->ERQ = 0U;
126 base->INT = 0xFFFFFFFFU;
127 base->ERR = 0xFFFFFFFFU;
128 /* Configure EDMA peripheral according to the configuration structure. */
129 tmpreg = base->CR;
130 tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
131 tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
132 DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
133 base->CR = tmpreg;
134}
static void CLOCK_EnableClock(clock_ip_name_t name)
Enable the clock for specific IP.
Definition fsl_clock.h:641

Referenced by dmaInit().

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◆ EDMA_InstallTCD()

void EDMA_InstallTCD ( DMA_Type *  base,
uint32_t  channel,
edma_tcd_t tcd 
)

Push content of TCD structure into hardware TCD register.

Parameters
baseEDMA peripheral base address.
channelEDMA channel number.
tcdPoint to TCD structure.

brief Push content of TCD structure into hardware TCD register.

param base EDMA peripheral base address. param channel EDMA channel number. param tcd Point to TCD structure.

Definition at line 81 of file fsl_edma.c.

82{
83 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
84 assert(tcd != NULL);
85 assert(((uint32_t)tcd & 0x1FU) == 0);
86
87 /* Push tcd into hardware TCD register */
88 base->TCD[channel].SADDR = tcd->SADDR;
89 base->TCD[channel].SOFF = tcd->SOFF;
90 base->TCD[channel].ATTR = tcd->ATTR;
91 base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
92 base->TCD[channel].SLAST = tcd->SLAST;
93 base->TCD[channel].DADDR = tcd->DADDR;
94 base->TCD[channel].DOFF = tcd->DOFF;
95 base->TCD[channel].CITER_ELINKNO = tcd->CITER;
96 base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
97 /* Clear DONE bit first, otherwise ESG cannot be set */
98 base->TCD[channel].CSR = 0;
99 base->TCD[channel].CSR = tcd->CSR;
100 base->TCD[channel].BITER_ELINKNO = tcd->BITER;
101}

Referenced by EDMA_SubmitTransfer().

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◆ EDMA_InstallTCDMemory()

void EDMA_InstallTCDMemory ( edma_handle_t handle,
edma_tcd_t tcdPool,
uint32_t  tcdSize 
)

Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

Parameters
handleeDMA handle pointer.
tcdPoolA memory pool to store TCDs. It must be 32 bytes aligned.
tcdSizeThe number of TCD slots.

brief Installs the TCDs memory pool into the eDMA handle.

This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.

param handle eDMA handle pointer. param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. param tcdSize The number of TCD slots.

Definition at line 812 of file fsl_edma.c.

813{
814 assert(handle != NULL);
815 assert(((uint32_t)tcdPool & 0x1FU) == 0);
816
817 /* Initialize tcd queue attribute. */
818 handle->header = 0;
819 handle->tail = 0;
820 handle->tcdUsed = 0;
821 handle->tcdSize = tcdSize;
822 handle->flags = 0;
823 handle->tcdPool = tcdPool;
824}
uint8_t flags
Definition fsl_edma.h:257

◆ EDMA_PrepareTransfer()

void EDMA_PrepareTransfer ( edma_transfer_config_t config,
void *  srcAddr,
uint32_t  srcWidth,
void *  destAddr,
uint32_t  destWidth,
uint32_t  bytesEachRequest,
uint32_t  transferBytes,
edma_transfer_type_t  type 
)

Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

Parameters
configThe user configuration structure of type edma_transfer_t.
srcAddreDMA transfer source address.
srcWidtheDMA transfer source address width(bytes).
destAddreDMA transfer destination address.
destWidtheDMA transfer destination address width(bytes).
bytesEachRequesteDMA transfer bytes per channel request.
transferByteseDMA transfer bytes to be transferred.
typeeDMA transfer type.
Note
The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

brief Prepares the eDMA transfer structure.

This function prepares the transfer configuration structure according to the user input.

param config The user configuration structure of type edma_transfer_t. param srcAddr eDMA transfer source address. param srcWidth eDMA transfer source address width(bytes). param destAddr eDMA transfer destination address. param destWidth eDMA transfer destination address width(bytes). param bytesEachRequest eDMA transfer bytes per channel request. param transferBytes eDMA transfer bytes to be transferred. param type eDMA transfer type. note The data address and the data width must be consistent. For example, if the SRC is 4 bytes, the source address must be 4 bytes aligned, or it results in source address error (SAE).

Definition at line 861 of file fsl_edma.c.

869{
870 assert(config != NULL);
871 assert(srcAddr != NULL);
872 assert(destAddr != NULL);
873 assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
874 assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
875 assert(transferBytes % bytesEachRequest == 0);
876
877 /* Initializes the configure structure to zero. */
878 memset(config, 0, sizeof(*config));
879
880 config->destAddr = (uint32_t)destAddr;
881 config->srcAddr = (uint32_t)srcAddr;
882 config->minorLoopBytes = bytesEachRequest;
883 config->majorLoopCounts = transferBytes / bytesEachRequest;
884 switch (srcWidth)
885 {
886 case 1U:
887 config->srcTransferSize = kEDMA_TransferSize1Bytes;
888 break;
889 case 2U:
890 config->srcTransferSize = kEDMA_TransferSize2Bytes;
891 break;
892 case 4U:
893 config->srcTransferSize = kEDMA_TransferSize4Bytes;
894 break;
895 case 16U:
896 config->srcTransferSize = kEDMA_TransferSize16Bytes;
897 break;
898 case 32U:
899 config->srcTransferSize = kEDMA_TransferSize32Bytes;
900 break;
901 default:
902 break;
903 }
904 switch (destWidth)
905 {
906 case 1U:
907 config->destTransferSize = kEDMA_TransferSize1Bytes;
908 break;
909 case 2U:
910 config->destTransferSize = kEDMA_TransferSize2Bytes;
911 break;
912 case 4U:
913 config->destTransferSize = kEDMA_TransferSize4Bytes;
914 break;
915 case 16U:
916 config->destTransferSize = kEDMA_TransferSize16Bytes;
917 break;
918 case 32U:
919 config->destTransferSize = kEDMA_TransferSize32Bytes;
920 break;
921 default:
922 break;
923 }
924 switch (type)
925 {
927 config->destOffset = destWidth;
928 config->srcOffset = srcWidth;
929 break;
931 config->destOffset = 0U;
932 config->srcOffset = srcWidth;
933 break;
935 config->destOffset = destWidth;
936 config->srcOffset = 0U;
937 break;
938 default:
939 break;
940 }
941}

Referenced by LPUART_ReceiveEDMA(), and LPUART_SendEDMA().

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◆ EDMA_ResetChannel()

void EDMA_ResetChannel ( DMA_Type *  base,
uint32_t  channel 
)

Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
Note
This function must not be called while the channel transfer is ongoing or it causes unpredictable results.
This function enables the auto stop request feature.

brief Sets all TCD registers to default values.

This function sets TCD registers for this channel to default values.

param base eDMA peripheral base address. param channel eDMA channel number. note This function must not be called while the channel transfer is ongoing or it causes unpredictable results. note This function enables the auto stop request feature.

Definition at line 189 of file fsl_edma.c.

190{
191 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
192
193 EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
194}
void EDMA_TcdReset(edma_tcd_t *tcd)
Sets all fields to default values for the TCD structure.
Definition fsl_edma.c:392

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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◆ EDMA_SetBandWidth()

void EDMA_SetBandWidth ( DMA_Type *  base,
uint32_t  channel,
edma_bandwidth_t  bandWidth 
)

Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
bandWidthA bandwidth setting, which can be one of the following:
  • kEDMABandwidthStallNone
  • kEDMABandwidthStall4Cycle
  • kEDMABandwidthStall8Cycle
brief Sets the bandwidth for the eDMA transfer.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

param base eDMA peripheral base address. param channel eDMA channel number. param bandWidth A bandwidth setting, which can be one of the following: arg kEDMABandwidthStallNone arg kEDMABandwidthStall4Cycle arg kEDMABandwidthStall8Cycle

Definition at line 293 of file fsl_edma.c.

294{
295 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
296
297 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
298}

◆ EDMA_SetCallback()

void EDMA_SetCallback ( edma_handle_t handle,
edma_callback  callback,
void *  userData 
)

Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

Parameters
handleeDMA handle pointer.
callbackeDMA callback function pointer.
userDataA parameter for the callback function.

brief Installs a callback function for the eDMA transfer.

This callback is called in the eDMA IRQ handler. Use the callback to do something after the current major loop transfer completes. This function will be called every time one tcd finished transfer.

param handle eDMA handle pointer. param callback eDMA callback function pointer. param userData A parameter for the callback function.

Definition at line 836 of file fsl_edma.c.

837{
838 assert(handle != NULL);
839
840 handle->callback = callback;
841 handle->userData = userData;
842}

Referenced by LPSPI_MasterTransferEDMA(), LPSPI_SlaveTransferEDMA(), and LPUART_TransferCreateHandleEDMA().

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◆ EDMA_SetChannelLink()

void EDMA_SetChannelLink ( DMA_Type *  base,
uint32_t  channel,
edma_channel_link_type_t  type,
uint32_t  linkedChannel 
)

Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
typeA channel link type, which can be one of the following:
  • kEDMA_LinkNone
  • kEDMA_MinorLink
  • kEDMA_MajorLink
linkedChannelThe linked channel number.
Note
Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

brief Sets the channel link for the eDMA transfer.

This function configures either the minor link or the major link mode. The minor link means that the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

param base eDMA peripheral base address. param channel eDMA channel number. param type A channel link type, which can be one of the following: arg kEDMA_LinkNone arg kEDMA_MinorLink arg kEDMA_MajorLink param linkedChannel The linked channel number. note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.

Definition at line 271 of file fsl_edma.c.

272{
273 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
274 assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
275
276 EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
277}
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
Sets the channel link for the eDMA TCD.
Definition fsl_edma.c:518
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◆ EDMA_SetChannelPreemptionConfig()

static void EDMA_SetChannelPreemptionConfig ( DMA_Type *  base,
uint32_t  channel,
const edma_channel_Preemption_config_t config 
)
inlinestatic

Configures the eDMA channel preemption feature.

This function configures the channel preemption attribute and the priority of the channel.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number
configA pointer to the channel preemption configuration structure.

Definition at line 388 of file fsl_edma.h.

391{
392 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
393 assert(config != NULL);
394
395 DMA_DCHPRIn(base, channel) =
396 (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) |
397 DMA_DCHPRI0_CHPRI(config->channelPriority));
398}

◆ EDMA_SetMinorOffsetConfig()

void EDMA_SetMinorOffsetConfig ( DMA_Type *  base,
uint32_t  channel,
const edma_minor_offset_config_t config 
)

Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
configA pointer to the minor offset configuration structure.

brief Configures the eDMA minor offset feature.

The minor offset means that the signed-extended value is added to the source address or destination address after each minor loop.

param base eDMA peripheral base address. param channel eDMA channel number. param config A pointer to the minor offset configuration structure.

Definition at line 240 of file fsl_edma.c.

241{
242 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
243 assert(config != NULL);
244
245 uint32_t tmpreg;
246
247 tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
248 tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
249 tmpreg |=
250 (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
251 DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
252 base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
253}

◆ EDMA_SetModulo()

void EDMA_SetModulo ( DMA_Type *  base,
uint32_t  channel,
edma_modulo_t  srcModulo,
edma_modulo_t  destModulo 
)

Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
srcModuloA source modulo value.
destModuloA destination modulo value.

brief Sets the source modulo and the destination modulo for the eDMA transfer.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

param base eDMA peripheral base address. param channel eDMA channel number. param srcModulo A source modulo value. param destModulo A destination modulo value.

Definition at line 312 of file fsl_edma.c.

313{
314 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
315
316 uint32_t tmpreg;
317
318 tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
319 base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
320}

◆ EDMA_SetTransferConfig()

void EDMA_SetTransferConfig ( DMA_Type *  base,
uint32_t  channel,
const edma_transfer_config_t config,
edma_tcd_t nextTcd 
)

Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example:

edma_transfer_t config;
config.srcAddr = ..;
config.destAddr = ..;
...
EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
Parameters
baseeDMA peripheral base address.
channeleDMA channel number.
configPointer to eDMA transfer configuration structure.
nextTcdPoint to TCD structure. It can be NULL if users do not want to enable scatter/gather feature.
Note
If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

brief Configures the eDMA transfer attribute.

This function configures the transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the TCD address. Example: code edma_transfer_t config; edma_tcd_t tcd; config.srcAddr = ..; config.destAddr = ..; ... EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); endcode

param base eDMA peripheral base address. param channel eDMA channel number. param config Pointer to eDMA transfer configuration structure. param nextTcd Point to TCD structure. It can be NULL if users do not want to enable scatter/gather feature. note If nextTcd is not NULL, it means scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the eDMA_ResetChannel.

Definition at line 221 of file fsl_edma.c.

222{
223 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
224 assert(config != NULL);
225 assert(((uint32_t)nextTcd & 0x1FU) == 0);
226
227 EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
228}
void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Configures the eDMA TCD transfer attribute.
Definition fsl_edma.c:439

Referenced by EDMA_SubmitTransfer(), LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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◆ EDMA_StartTransfer()

void EDMA_StartTransfer ( edma_handle_t handle)

eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

Parameters
handleeDMA handle pointer.

brief eDMA starts transfer.

This function enables the channel request. Users can call this function after submitting the transfer request or before submitting the transfer request.

param handle eDMA handle pointer.

Definition at line 1103 of file fsl_edma.c.

1104{
1105 assert(handle != NULL);
1106
1107 if (handle->tcdPool == NULL)
1108 {
1109 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
1110 }
1111 else /* Use the TCD queue. */
1112 {
1113 uint32_t primask;
1114 edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
1115
1116 handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
1117
1118 /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
1119 if (tcdRegs->DLAST_SGA != 0U)
1120 {
1121 primask = DisableGlobalIRQ();
1122 /* Check if channel request is actually disable. */
1123 if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
1124 {
1125 /* Check if transfer is paused. */
1126 if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
1127 {
1128 /*
1129 Re-enable channel request must be as soon as possible, so must put it into
1130 critical section to avoid task switching or interrupt service routine.
1131 */
1132 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
1133 }
1134 }
1135 EnableGlobalIRQ(primask);
1136 }
1137 }
1138}

Referenced by LPSPI_MasterTransferEDMA(), LPSPI_SlaveTransferEDMA(), LPUART_ReceiveEDMA(), and LPUART_SendEDMA().

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◆ EDMA_StopTransfer()

void EDMA_StopTransfer ( edma_handle_t handle)

eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

Parameters
handleeDMA handle pointer.

brief eDMA stops transfer.

This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() again to resume the transfer.

param handle eDMA handle pointer.

Definition at line 1148 of file fsl_edma.c.

1149{
1150 assert(handle != NULL);
1151
1152 handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
1153 handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
1154}

◆ EDMA_SubmitTransfer()

status_t EDMA_SubmitTransfer ( edma_handle_t handle,
const edma_transfer_config_t config 
)

Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

Parameters
handleeDMA handle pointer.
configPointer to eDMA transfer configuration structure.
Return values
kStatus_EDMA_SuccessIt means submit transfer request succeed.
kStatus_EDMA_QueueFullIt means TCD queue is full. Submit transfer request is not allowed.
kStatus_EDMA_BusyIt means the given channel is busy, need to submit request later.

brief Submits the eDMA transfer request.

This function submits the eDMA transfer request according to the transfer configuration structure. In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. The tcd pools is setup by call function EDMA_InstallTCDMemory before.

param handle eDMA handle pointer. param config Pointer to eDMA transfer configuration structure. retval kStatus_EDMA_Success It means submit transfer request succeed. retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.

Definition at line 956 of file fsl_edma.c.

957{
958 assert(handle != NULL);
959 assert(config != NULL);
960
961 edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
962
963 if (handle->tcdPool == NULL)
964 {
965 /*
966 Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
967 if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
968 this check mechanism, EDMA_CreatHandle will clear CSR register.
969 */
970 if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
971 {
972 return kStatus_EDMA_Busy;
973 }
974 else
975 {
976 EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL);
977 /* Enable auto disable request feature */
978 handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK;
979 /* Enable major interrupt */
980 handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK;
981
982 return kStatus_Success;
983 }
984 }
985 else /* Use the TCD queue. */
986 {
987 uint32_t primask;
988 uint32_t csr;
989 int8_t currentTcd;
990 int8_t previousTcd;
991 int8_t nextTcd;
992
993 /* Check if tcd pool is full. */
994 primask = DisableGlobalIRQ();
995 if (handle->tcdUsed >= handle->tcdSize)
996 {
997 EnableGlobalIRQ(primask);
998
1000 }
1001 currentTcd = handle->tail;
1002 handle->tcdUsed++;
1003 /* Calculate index of next TCD */
1004 nextTcd = currentTcd + 1U;
1005 if (nextTcd == handle->tcdSize)
1006 {
1007 nextTcd = 0U;
1008 }
1009 /* Advance queue tail index */
1010 handle->tail = nextTcd;
1011 EnableGlobalIRQ(primask);
1012 /* Calculate index of previous TCD */
1013 previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
1014 /* Configure current TCD block. */
1015 EDMA_TcdReset(&handle->tcdPool[currentTcd]);
1016 EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
1017 /* Enable major interrupt */
1018 handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
1019 /* Link current TCD with next TCD for identification of current TCD */
1020 handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
1021 /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
1022 if (currentTcd != previousTcd)
1023 {
1024 /* Enable scatter/gather feature in the previous TCD block. */
1025 csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
1026 handle->tcdPool[previousTcd].CSR = csr;
1027 /*
1028 Check if the TCD block in the registers is the previous one (points to current TCD block). It
1029 is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
1030 link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
1031 before link the previous TCD block.
1032 */
1033 if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
1034 {
1035 /* Clear the DREQ bits for the dynamic scatter gather */
1036 tcdRegs->CSR |= DMA_CSR_DREQ_MASK;
1037 /* Enable scatter/gather also in the TCD registers. */
1038 csr = tcdRegs->CSR | DMA_CSR_ESG_MASK;
1039 /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
1040 tcdRegs->CSR = csr;
1041 /*
1042 It is very important to check the ESG bit!
1043 Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
1044 be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
1045 and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
1046 the current TCD block has been loaded into TCD registers), it means transfer finished
1047 and TCD link operation fail, so must install TCD content into TCD registers and enable
1048 transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic
1049 link succeed.
1050 */
1051 if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
1052 {
1053 tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
1054 return kStatus_Success;
1055 }
1056 /*
1057 Check whether the current TCD block is already loaded in the TCD registers. It is another
1058 condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
1059 TCD block has been loaded into TCD registers.
1060 */
1061 if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
1062 {
1063 return kStatus_Success;
1064 }
1065 /*
1066 If go to this, means the previous transfer finished, and the DONE bit is set.
1067 So shall configure TCD registers.
1068 */
1069 }
1070 else if (tcdRegs->DLAST_SGA != 0)
1071 {
1072 /* The current TCD block has been linked successfully. */
1073 return kStatus_Success;
1074 }
1075 else
1076 {
1077 /*
1078 DLAST_SGA is 0 and it means the first submit transfer, so shall configure
1079 TCD registers.
1080 */
1081 }
1082 }
1083 /* There is no live chain, TCD block need to be installed in TCD registers. */
1084 EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
1085 /* Enable channel request again. */
1086 if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
1087 {
1088 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
1089 }
1090
1091 return kStatus_Success;
1092 }
1093}
void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
Push content of TCD structure into hardware TCD register.
Definition fsl_edma.c:81
void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
Configures the eDMA transfer attribute.
Definition fsl_edma.c:221
@ kStatus_Success
Definition fsl_common.h:159

Referenced by LPUART_ReceiveEDMA(), and LPUART_SendEDMA().

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◆ EDMA_TcdDisableInterrupts()

void EDMA_TcdDisableInterrupts ( edma_tcd_t tcd,
uint32_t  mask 
)

Disables the interrupt source for the eDMA TCD.

Parameters
tcdPoint to the TCD structure.
maskThe mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

brief Disables the interrupt source for the eDMA TCD.

param tcd Point to the TCD structure. param mask The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

Definition at line 610 of file fsl_edma.c.

611{
612 assert(tcd != NULL);
613
614 /* Disable Major interrupt */
616 {
617 tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
618 }
619
620 /* Disable Half major interrupt */
621 if (mask & kEDMA_HalfInterruptEnable)
622 {
623 tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
624 }
625}

◆ EDMA_TcdEnableAutoStopRequest()

static void EDMA_TcdEnableAutoStopRequest ( edma_tcd_t tcd,
bool  enable 
)
inlinestatic

Sets the auto stop request for the eDMA TCD.

If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.

Parameters
tcdA pointer to the TCD structure.
enableThe command to enable (true) or disable (false).

Definition at line 614 of file fsl_edma.h.

615{
616 assert(tcd != NULL);
617 assert(((uint32_t)tcd & 0x1FU) == 0);
618
619 tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable);
620}
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◆ EDMA_TcdEnableInterrupts()

void EDMA_TcdEnableInterrupts ( edma_tcd_t tcd,
uint32_t  mask 
)

Enables the interrupt source for the eDMA TCD.

Parameters
tcdPoint to the TCD structure.
maskThe mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

brief Enables the interrupt source for the eDMA TCD.

param tcd Point to the TCD structure. param mask The mask of interrupt source to be set. Users need to use the defined edma_interrupt_enable_t type.

Definition at line 586 of file fsl_edma.c.

587{
588 assert(tcd != NULL);
589
590 /* Enable Major interrupt */
592 {
593 tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
594 }
595
596 /* Enable Half major interrupt */
597 if (mask & kEDMA_HalfInterruptEnable)
598 {
599 tcd->CSR |= DMA_CSR_INTHALF_MASK;
600 }
601}

◆ EDMA_TcdReset()

void EDMA_TcdReset ( edma_tcd_t tcd)

Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

Parameters
tcdPointer to the TCD structure.
Note
This function enables the auto stop request feature.

brief Sets all fields to default values for the TCD structure.

This function sets all fields for this TCD structure to default value.

param tcd Pointer to the TCD structure. note This function enables the auto stop request feature.

Definition at line 392 of file fsl_edma.c.

393{
394 assert(tcd != NULL);
395 assert(((uint32_t)tcd & 0x1FU) == 0);
396
397 /* Reset channel TCD */
398 tcd->SADDR = 0U;
399 tcd->SOFF = 0U;
400 tcd->ATTR = 0U;
401 tcd->NBYTES = 0U;
402 tcd->SLAST = 0U;
403 tcd->DADDR = 0U;
404 tcd->DOFF = 0U;
405 tcd->CITER = 0U;
406 tcd->DLAST_SGA = 0U;
407 /* Enable auto disable request feature */
408 tcd->CSR = DMA_CSR_DREQ(true);
409 tcd->BITER = 0U;
410}

Referenced by EDMA_ResetChannel(), EDMA_SubmitTransfer(), LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

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◆ EDMA_TcdSetBandWidth()

static void EDMA_TcdSetBandWidth ( edma_tcd_t tcd,
edma_bandwidth_t  bandWidth 
)
inlinestatic

Sets the bandwidth for the eDMA TCD.

Because the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch.

Parameters
tcdA pointer to the TCD structure.
bandWidthA bandwidth setting, which can be one of the following:
  • kEDMABandwidthStallNone
  • kEDMABandwidthStall4Cycle
  • kEDMABandwidthStall8Cycle

Definition at line 585 of file fsl_edma.h.

586{
587 assert(tcd != NULL);
588 assert(((uint32_t)tcd & 0x1FU) == 0);
589
590 tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
591}

◆ EDMA_TcdSetChannelLink()

void EDMA_TcdSetChannelLink ( edma_tcd_t tcd,
edma_channel_link_type_t  type,
uint32_t  linkedChannel 
)

Sets the channel link for the eDMA TCD.

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

Note
Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
Parameters
tcdPoint to the TCD structure.
typeChannel link type, it can be one of:
  • kEDMA_LinkNone
  • kEDMA_MinorLink
  • kEDMA_MajorLink
linkedChannelThe linked channel number.

brief Sets the channel link for the eDMA TCD.

This function configures either a minor link or a major link. The minor link means the channel link is triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.

note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. param tcd Point to the TCD structure. param type Channel link type, it can be one of: arg kEDMA_LinkNone arg kEDMA_MinorLink arg kEDMA_MajorLink param linkedChannel The linked channel number.

Definition at line 518 of file fsl_edma.c.

519{
520 assert(tcd != NULL);
521 assert(((uint32_t)tcd & 0x1FU) == 0);
522 assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
523
524 if (type == kEDMA_MinorLink) /* Minor link config */
525 {
526 uint32_t tmpreg;
527
528 /* Enable minor link */
529 tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
530 tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
531 /* Set linked channel */
532 tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
533 tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
534 tcd->CITER = tmpreg;
535 tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
536 tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
537 tcd->BITER = tmpreg;
538 }
539 else if (type == kEDMA_MajorLink) /* Major link config */
540 {
541 uint32_t tmpreg;
542
543 /* Enable major link */
544 tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
545 /* Set major linked channel */
546 tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
547 tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
548 }
549 else /* Link none */
550 {
551 tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
552 tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
553 tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
554 }
555}

Referenced by EDMA_SetChannelLink().

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◆ EDMA_TcdSetMinorOffsetConfig()

void EDMA_TcdSetMinorOffsetConfig ( edma_tcd_t tcd,
const edma_minor_offset_config_t config 
)

Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

Parameters
tcdA point to the TCD structure.
configA pointer to the minor offset configuration structure.

brief Configures the eDMA TCD minor offset feature.

A minor offset is a signed-extended value added to the source address or a destination address after each minor loop.

param tcd A point to the TCD structure. param config A pointer to the minor offset configuration structure.

Definition at line 488 of file fsl_edma.c.

489{
490 assert(tcd != NULL);
491 assert(((uint32_t)tcd & 0x1FU) == 0);
492
493 uint32_t tmpreg;
494
495 tmpreg = tcd->NBYTES &
496 ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
497 tmpreg |=
498 (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
499 DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
500 tcd->NBYTES = tmpreg;
501}

◆ EDMA_TcdSetModulo()

void EDMA_TcdSetModulo ( edma_tcd_t tcd,
edma_modulo_t  srcModulo,
edma_modulo_t  destModulo 
)

Sets the source modulo and the destination modulo for the eDMA TCD.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

Parameters
tcdA pointer to the TCD structure.
srcModuloA source modulo value.
destModuloA destination modulo value.

brief Sets the source modulo and the destination modulo for the eDMA TCD.

This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) calculation is performed or the original register value. It provides the ability to implement a circular data queue easily.

param tcd A pointer to the TCD structure. param srcModulo A source modulo value. param destModulo A destination modulo value.

Definition at line 568 of file fsl_edma.c.

569{
570 assert(tcd != NULL);
571 assert(((uint32_t)tcd & 0x1FU) == 0);
572
573 uint32_t tmpreg;
574
575 tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
576 tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
577}

◆ EDMA_TcdSetTransferConfig()

void EDMA_TcdSetTransferConfig ( edma_tcd_t tcd,
const edma_transfer_config_t config,
edma_tcd_t nextTcd 
)

Configures the eDMA TCD transfer attribute.

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The STCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example:

edma_transfer_t config = {
...
}
edma_tcd_t tcd __aligned(32);
edma_tcd_t nextTcd __aligned(32);
Parameters
tcdPointer to the TCD structure.
configPointer to eDMA transfer configuration structure.
nextTcdPointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature.
Note
TCD address should be 32 bytes aligned or it causes an eDMA error.
If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

brief Configures the eDMA TCD transfer attribute.

The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. The STCD is used in the scatter-gather mode. This function configures the TCD transfer attribute, including source address, destination address, transfer size, address offset, and so on. It also configures the scatter gather feature if the user supplies the next TCD address. Example: code edma_transfer_t config = { ... } edma_tcd_t tcd __aligned(32); edma_tcd_t nextTcd __aligned(32); EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); endcode

param tcd Pointer to the TCD structure. param config Pointer to eDMA transfer configuration structure. param nextTcd Pointer to the next TCD structure. It can be NULL if users do not want to enable scatter/gather feature. note TCD address should be 32 bytes aligned or it causes an eDMA error. note If the nextTcd is not NULL, the scatter gather feature is enabled and DREQ bit is cleared in the previous transfer configuration, which is set in the EDMA_TcdReset.

Definition at line 439 of file fsl_edma.c.

440{
441 assert(tcd != NULL);
442 assert(((uint32_t)tcd & 0x1FU) == 0);
443 assert(config != NULL);
444 assert(((uint32_t)nextTcd & 0x1FU) == 0);
445
446 /* source address */
447 tcd->SADDR = config->srcAddr;
448 /* destination address */
449 tcd->DADDR = config->destAddr;
450 /* Source data and destination data transfer size */
451 tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
452 /* Source address signed offset */
453 tcd->SOFF = config->srcOffset;
454 /* Destination address signed offset */
455 tcd->DOFF = config->destOffset;
456 /* Minor byte transfer count */
457 tcd->NBYTES = config->minorLoopBytes;
458 /* Current major iteration count */
459 tcd->CITER = config->majorLoopCounts;
460 /* Starting major iteration count */
461 tcd->BITER = config->majorLoopCounts;
462 /* Enable scatter/gather processing */
463 if (nextTcd != NULL)
464 {
465 tcd->DLAST_SGA = (uint32_t)nextTcd;
466 /*
467 Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
468 user must call EDMA_TcdReset or EDMA_ResetChannel which will set
469 DREQ, so must use "|" or "&" rather than "=".
470
471 Clear the DREQ bit because scatter gather has been enabled, so the
472 previous transfer is not the last transfer, and channel request should
473 be enabled at the next transfer(the next TCD).
474 */
475 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
476 }
477}

Referenced by EDMA_SetTransferConfig(), EDMA_SubmitTransfer(), LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

Here is the caller graph for this function:

◆ EDMA_TriggerChannelStart()

static void EDMA_TriggerChannelStart ( DMA_Type *  base,
uint32_t  channel 
)
inlinestatic

Starts the eDMA transfer by using the software trigger.

This function starts a minor loop transfer.

Parameters
baseeDMA peripheral base address.
channeleDMA channel number.

Definition at line 684 of file fsl_edma.h.

685{
686 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
687
688 base->SSRT = DMA_SSRT_SSRT(channel);
689}

Variable Documentation

◆ ATTR

__IO uint16_t _edma_tcd::ATTR

ATTR register, source/destination transfer size and modulo

Definition at line 210 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), EDMA_TcdSetModulo(), and EDMA_TcdSetTransferConfig().

◆ base

DMA_Type* _edma_handle::base

◆ BITER

__IO uint16_t _edma_tcd::BITER

BITER register, begin minor loop count.

Definition at line 218 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), EDMA_TcdSetChannelLink(), and EDMA_TcdSetTransferConfig().

◆ callback

edma_callback _edma_handle::callback

Callback function for major count exhausted.

Definition at line 247 of file fsl_edma.h.

Referenced by EDMA_HandleIRQ(), and EDMA_SetCallback().

◆ channel

uint8_t _edma_handle::channel

◆ channelPriority

uint8_t _edma_channel_Preemption_config::channelPriority

Channel priority

Definition at line 189 of file fsl_edma.h.

◆ CITER

__IO uint16_t _edma_tcd::CITER

CITER register, current minor loop numbers, for unfinished minor loop.

Definition at line 215 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), EDMA_TcdSetChannelLink(), and EDMA_TcdSetTransferConfig().

◆ CSR

__IO uint16_t _edma_tcd::CSR

◆ DADDR

__IO uint32_t _edma_tcd::DADDR

DADDR register, used for destination address

Definition at line 213 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), and EDMA_TcdSetTransferConfig().

◆ destAddr

uint32_t _edma_transfer_config::destAddr

Destination data address.

Definition at line 173 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ destOffset

int16_t _edma_transfer_config::destOffset

Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed.

Definition at line 178 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ destTransferSize

edma_transfer_size_t _edma_transfer_config::destTransferSize

Destination data transfer size.

Definition at line 175 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ DLAST_SGA

__IO uint32_t _edma_tcd::DLAST_SGA

DLASTSGA register, next tcd address used in scatter-gather mode

Definition at line 216 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_StartTransfer(), EDMA_SubmitTransfer(), EDMA_TcdReset(), and EDMA_TcdSetTransferConfig().

◆ DOFF

__IO uint16_t _edma_tcd::DOFF

DOFF register, used for destination offset

Definition at line 214 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), and EDMA_TcdSetTransferConfig().

◆ enableChannelPreemption

bool _edma_channel_Preemption_config::enableChannelPreemption

If true: a channel can be suspended by other channel with higher priority

Definition at line 187 of file fsl_edma.h.

◆ enableContinuousLinkMode

bool _edma_config::enableContinuousLinkMode

Enable (true) continuous link mode. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself.

Definition at line 154 of file fsl_edma.h.

◆ enableDebugMode

bool _edma_config::enableDebugMode

Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of a new channel. Executing channels are allowed to complete.

Definition at line 161 of file fsl_edma.h.

◆ enableDestMinorOffset

bool _edma_minor_offset_config::enableDestMinorOffset

Enable(true) or Disable(false) destination minor loop offset.

Definition at line 196 of file fsl_edma.h.

◆ enableHaltOnError

bool _edma_config::enableHaltOnError

Enable (true) transfer halt on error. Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

Definition at line 157 of file fsl_edma.h.

Referenced by dmaInit().

◆ enablePreemptAbility

bool _edma_channel_Preemption_config::enablePreemptAbility

If true: a channel can suspend other channel with low priority

Definition at line 188 of file fsl_edma.h.

◆ enableRoundRobinArbitration

bool _edma_config::enableRoundRobinArbitration

Enable (true) round robin channel arbitration method or fixed priority arbitration is used for channel selection

Definition at line 159 of file fsl_edma.h.

◆ enableSrcMinorOffset

bool _edma_minor_offset_config::enableSrcMinorOffset

Enable(true) or Disable(false) source minor loop offset.

Definition at line 195 of file fsl_edma.h.

◆ flags

uint8_t _edma_handle::flags

The status of the current channel.

Definition at line 257 of file fsl_edma.h.

Referenced by EDMA_InstallTCDMemory(), EDMA_StartTransfer(), EDMA_StopTransfer(), and EDMA_SubmitTransfer().

◆ header

volatile int8_t _edma_handle::header

The first TCD index. Should point to the next TCD to be loaded into the eDMA engine.

Definition at line 252 of file fsl_edma.h.

Referenced by EDMA_AbortTransfer(), EDMA_HandleIRQ(), and EDMA_InstallTCDMemory().

◆ majorLoopCounts

uint32_t _edma_transfer_config::majorLoopCounts

Major loop iteration count.

Definition at line 181 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ minorLoopBytes

uint32_t _edma_transfer_config::minorLoopBytes

Bytes to transfer in a minor loop

Definition at line 180 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ minorOffset

uint32_t _edma_minor_offset_config::minorOffset

Offset for a minor loop mapping.

Definition at line 197 of file fsl_edma.h.

◆ NBYTES

__IO uint32_t _edma_tcd::NBYTES

Nbytes register, minor loop length in bytes

Definition at line 211 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), EDMA_TcdSetMinorOffsetConfig(), and EDMA_TcdSetTransferConfig().

◆ SADDR

__IO uint32_t _edma_tcd::SADDR

SADDR register, used to save source address

Definition at line 208 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), and EDMA_TcdSetTransferConfig().

◆ SLAST

__IO uint32_t _edma_tcd::SLAST

SLAST register

Definition at line 212 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), and EDMA_TcdReset().

◆ SOFF

__IO uint16_t _edma_tcd::SOFF

SOFF register, save offset bytes every transfer

Definition at line 209 of file fsl_edma.h.

Referenced by EDMA_CreateHandle(), EDMA_InstallTCD(), EDMA_TcdReset(), and EDMA_TcdSetTransferConfig().

◆ srcAddr

uint32_t _edma_transfer_config::srcAddr

Source data address.

Definition at line 172 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ srcOffset

int16_t _edma_transfer_config::srcOffset

Sign-extended offset applied to the current source address to form the next-state value as each source read is completed.

Definition at line 176 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ srcTransferSize

edma_transfer_size_t _edma_transfer_config::srcTransferSize

Source data transfer size.

Definition at line 174 of file fsl_edma.h.

Referenced by LPSPI_MasterTransferEDMA(), and LPSPI_SlaveTransferEDMA().

◆ tail

volatile int8_t _edma_handle::tail

The last TCD index. Should point to the next TCD to be stored into the memory pool.

Definition at line 253 of file fsl_edma.h.

Referenced by EDMA_AbortTransfer(), EDMA_InstallTCDMemory(), and EDMA_SubmitTransfer().

◆ tcdPool

edma_tcd_t* _edma_handle::tcdPool

Pointer to memory stored TCDs.

Definition at line 250 of file fsl_edma.h.

Referenced by EDMA_AbortTransfer(), EDMA_HandleIRQ(), EDMA_InstallTCDMemory(), EDMA_StartTransfer(), and EDMA_SubmitTransfer().

◆ tcdSize

volatile int8_t _edma_handle::tcdSize

The total number of TCD slots in the queue.

Definition at line 256 of file fsl_edma.h.

Referenced by EDMA_GetUnusedTCDNumber(), EDMA_HandleIRQ(), EDMA_InstallTCDMemory(), and EDMA_SubmitTransfer().

◆ tcdUsed

volatile int8_t _edma_handle::tcdUsed

The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in the memory.

Definition at line 254 of file fsl_edma.h.

Referenced by EDMA_AbortTransfer(), EDMA_GetUnusedTCDNumber(), EDMA_HandleIRQ(), EDMA_InstallTCDMemory(), and EDMA_SubmitTransfer().

◆ userData

void* _edma_handle::userData

Callback function parameter.

Definition at line 248 of file fsl_edma.h.

Referenced by EDMA_HandleIRQ(), and EDMA_SetCallback().