113#ifdef _CHIBIOS_RT_CONF_VER_6_1_
127 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
131 .cr2 = SPI_CR2_16BIT_MODE
135 [0] = {.port = GPIOF, .pad = 12},
136 [1] = {.port = GPIOF, .pad = 13},
137 [2] = {.port = GPIOF, .pad = 14},
138 [3] = {.port = GPIOF, .pad = 15},
140 [4] = {.port = GPIOE, .pad = 8},
141 [5] = {.port = GPIOE, .pad = 9},
142 [6] = {.port = GPIOE, .pad = 10},
143 [7] = {.port = GPIOE, .pad = 11},
144 [8] = {.port = GPIOG, .pad = 5},
145 [9] = {.port = GPIOG, .pad = 6},
146 [10] = {.port = GPIOG, .pad = 7},
149 .pwm_gpio = {.port = NULL, .pad = 0}