149#ifdef _CHIBIOS_RT_CONF_VER_6_1_
162 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
166 .cr2 = SPI_CR2_16BIT_MODE
169 { .port = GPIOG, .pad = 7 },
170 { .port = GPIOG, .pad = 8 },
171 { .port = GPIOD, .pad = 11 },
172 { .port = GPIOD, .pad = 10 }
182#ifdef _CHIBIOS_RT_CONF_VER_6_1_
195 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
199 .cr2 = SPI_CR2_16BIT_MODE
202 { .port = GPIOD, .pad = 9 },
203 { .port = GPIOF, .pad = 12 },
204 { .port = GPIOF, .pad = 13 },
205 { .port = GPIOF, .pad = 14 }
215#ifdef _CHIBIOS_RT_CONF_VER_6_1_
228 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
232 .cr2 = SPI_CR2_16BIT_MODE
235 { .port = GPIOD, .pad = 3 },
236 { .port = GPIOA, .pad = 9 },
237 { .port = GPIOG, .pad = 14 },
238 { .port = GPIOG, .pad = 5 }
248#ifdef _CHIBIOS_RT_CONF_VER_6_1_
261 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
265 .cr2 = SPI_CR2_16BIT_MODE
268 { .port = GPIOD, .pad = 2 },
269 { .port = GPIOG, .pad = 11 },
270 { .port = GPIOG, .pad = 3 },
271 { .port = GPIOG, .pad = 4 }