252#ifdef _CHIBIOS_RT_CONF_VER_6_1_
265 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
274 SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0
278 [0] = {.port = GPIOI, .pad = 6},
279 [1] = {.port = GPIOI, .pad = 5},
280 [2] = {.port = GPIOI, .pad = 4},
281 [3] = {.port = GPIOB, .pad = 9},
283 [4] = {.port = GPIOB, .pad = 3},
284 [5] = {.port = GPIOB, .pad = 4},
285 [6] = {.port = GPIOB, .pad = 5},
286 [7] = {.port = GPIOB, .pad = 8},
289 .en = {.port = GPIOI, .pad = 7},
291 .sck = {.port = GPIOF, .pad = 7},
303#ifdef _CHIBIOS_RT_CONF_VER_6_1_
316 ((3 << SPI_CR1_BR_Pos) & SPI_CR1_BR) |
324 .cr2 = SPI_CR2_16BIT_MODE
328 [0] = {.port = GPIOE, .pad = 3},
329 [1] = {.port = GPIOE, .pad = 4},
330 [2] = {.port = GPIOE, .pad = 5},
331 [3] = {.port = GPIOE, .pad = 6},
333 [4] = {.port = GPIOI, .pad = 9},
334 [5] = {.port = GPIOC, .pad = 15},
335 [6] = {.port = GPIOC, .pad = 14},
336 [7] = {.port = GPIOC, .pad = 13},
339 .en = {.port =
nullptr, .pad = 0},
341 .sck = {.port = GPIOF, .pad = 7},